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1. 发明申请

US20050120337A1 Memory trace buffer 审中-公开
标题翻译：内存跟踪缓冲区
公开(公告)号：US20050120337A1
公开(公告)日：2005-06-02
申请号：US10725730
申请日：2003-12-01
申请人： Mauricio Serrano , Ali-Reza Adl-Tabatabai , Anwar Ghuloum , Dong-Yuan Chen , Richard Hudson
发明人： Mauricio Serrano , Ali-Reza Adl-Tabatabai , Anwar Ghuloum , Dong-Yuan Chen , Richard Hudson
IPC分类号： G06F9/44
CPC分类号： G06F11/28
摘要： According to an embodiment of the invention, a method and apparatus are described for memory trace buffering. An embodiment of a processor includes an execution unit and a buffer. The buffer is to store certain data regarding each memory operation of a plurality of memory operations that are executed by the processor.
摘要翻译：根据本发明的实施例，描述了一种用于存储器跟踪缓冲的方法和装置。处理器的实施例包括执行单元和缓冲器。缓冲器用于存储关于由处理器执行的多个存储器操作的每个存储器操作的某些数据。

2. 发明申请

US20050138329A1 Methods and apparatus to dynamically insert prefetch instructions based on garbage collector analysis and layout of objects 失效
标题翻译：基于垃圾回收器分析和对象布局动态插入预取指令的方法和装置
公开(公告)号：US20050138329A1
公开(公告)日：2005-06-23
申请号：US10741897
申请日：2003-12-19
申请人： Sreenivas Subramoney , Mauricio Serrano , Richard Hudson , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Mauricio Serrano , Richard Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F12/02 , G06F15/00
CPC分类号： G06F12/0253 , G06F12/0862 , G06F2212/6026
摘要： Methods and apparatus to dynamically insert prefetch instructions are disclosed. In an example method, one or more samples associated with cache misses are identified from a performance monitoring unit in a processor system. Based on sample information associated with the one or more samples, delinquent information is generated. To dynamically insert one or more prefetch instructions, a prefetch point is identified based on the delinquent information.
摘要翻译：公开了动态插入预取指令的方法和装置。在示例性方法中，与处理器系统中的性能监视单元识别与高速缓存未命中相关联的一个或多个样本。根据与一个或多个样本相关联的样本信息，生成违法信息。为了动态地插入一个或多个预取指令，基于拖欠信息来识别预取点。

3. 发明授权

US07490117B2 Dynamic performance monitoring-based approach to memory management 失效
标题翻译：基于动态性能监控的内存管理方法
公开(公告)号：US07490117B2
公开(公告)日：2009-02-10
申请号：US10749425
申请日：2003-12-31
申请人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/08
CPC分类号： G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
摘要： Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.
摘要翻译：描述了用于优化处理器系统中的存储器管理的技术。这些技术可以在包括片上性能监视的处理器以及外部性能监视器耦合到处理器的系统上实现。包括性能监控单元（PMU）的处理器就是例子。 PMU可以将数据存储在读取和写入高速缓存未命中，以及翻译后备缓冲区（TLB）未命中的数据。来自PMU的数据用于确定存储器堆中的任何存储器区域是否是过期存储器区域，即表现出大量存储器问题或失速的区域。如果发现存在不正当的内存区域，诸如垃圾收集例程的存储器管理器可以通过改进堆中对象的布局来有效地优化存储器性能以及突变器的性能。以这种方式，可以基于动态和实时存储器性能数据来集中存储器管理例程。

4. 发明申请

US20060143421A1 Dynamic performance monitoring-based approach to memory management 失效
公开(公告)号：US20060143421A1
公开(公告)日：2006-06-29
申请号：US10749425
申请日：2003-12-31
申请人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
发明人： Sreenivas Subramoney , Richard Hudson , Mauricio Serrano , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F11/348 , G06F12/0253 , G06F12/0269 , G06F2201/88 , G06F2201/885 , Y10S707/99957
摘要： Techniques are described for optimizing memory management in a processor system. The techniques may be implemented on processors that include on-chip performance monitoring and on systems where an external performance monitor is coupled to a processor. Processors that include a Performance Monitoring Unit (PMU) are examples. The PMU may store data on read and write cache misses, as well as data on translation lookaside buffer (TLB) misses. The data from the PMU is used to determine if any memory regions within a memory heap are delinquent memory regions, i.e., regions exhibiting high numbers of memory problems or stalls. If delinquent memory regions are found, the memory manager, such as a garbage collection routine, can efficiently optimize memory performance as well as the mutators performance by improving the layout of objects in the heap. In this way, memory management routines may be focused based on dynamic and real-time memory performance data.

5. 发明申请

US20050138294A1 Methods and apparatus to dynamically insert prefetch instructions based on compiler and garbage collector analysis 失效
标题翻译：基于编译器和垃圾回收器分析动态插入预取指令的方法和装置
公开(公告)号：US20050138294A1
公开(公告)日：2005-06-23
申请号：US10742009
申请日：2003-12-19
申请人： Mauricio Serrano , Sreenivas Subramoney , Richard Hudson , Ali-Reza Adl-Tabatabai
发明人： Mauricio Serrano , Sreenivas Subramoney , Richard Hudson , Ali-Reza Adl-Tabatabai
IPC分类号： G06F9/45 , G06F12/02 , G06F12/00
CPC分类号： G06F12/0253
摘要： Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
摘要翻译：公开了基于垃圾收集器分析和编译器分析来插入预取指令的方法和装置。在示例性方法中，接收与处理器系统中的来自性能监视单元的高速缓存未命中关联的一个或多个批次的样本。选择一个或多个基于犯罪信息的样本的一个或多个样本。产生与一个或多个样本相关联的性能影响指示符。基于性能指标，启动垃圾回收器分析和编译器分析中的至少一个以识别一个或多个违规路径。基于垃圾收集器分析和编译器分析中的至少一个，识别插入预取指令的一个或多个预取点。

6. 发明申请

US20070239974A1 System and method for target branch prediction using correlation of local target histories 失效
标题翻译：使用本地目标历史相关性进行目标分支预测的系统和方法
公开(公告)号：US20070239974A1
公开(公告)日：2007-10-11
申请号：US11399979
申请日：2006-04-07
申请人： II Park , Mauricio Serrano , Jong-Deok Choi
发明人： II Park , Mauricio Serrano , Jong-Deok Choi
IPC分类号： G06F15/00
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3848
摘要： An information processing system includes a branch target buffer (BTF) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potential branch targets based on a history of the branch and for providing an NBTT when the a BTB predicted target is not successful. In another embodiment a system comprising a plurality of branch prediction resources dynamically predicts the best resource appropriate for a branch. The method includes predicting a target branch for an indirect instruction address using a resource chosen among the plurality of branch prediction resources; and selectively inhibiting updates of the branch prediction resources whose prediction accuracy does not meet a threshold.
摘要翻译：信息处理系统包括分支目标缓冲器（BTF），该分支目标缓冲器包括用于该指令的最后一个下一个地址并用于接收一个间接指令地址并提供一个BTB预测目标; 以及用于基于分支的历史存储潜在的分支目标并且当BTB预测目标不成功时提供NBTT的下一分支目标表（NBTT）。在另一个实施例中，包括多个分支预测资源的系统动态地预测适合于分支的最佳资源。该方法包括使用在多个分支预测资源中选择的资源来预测间接指令地址的目标分支; 并且选择性地禁止预测精度不满足阈值的分支预测资源的更新。

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