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1. 发明授权

US09092253B2 Instrumentation of hardware assisted transactional memory system 有权
标题翻译：硬件辅助事务记忆体系统的设计
公开(公告)号：US09092253B2
公开(公告)日：2015-07-28
申请号：US12638345
申请日：2009-12-15
申请人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
发明人： Martin Taillefer , Jan Gray , Richard Wurdack , Gad Sheaffer , Ali-Reza Adl Tabatabai
IPC分类号： G06F9/44 , G06F9/46 , G06F11/36 , G06F11/34
CPC分类号： G06F9/467 , G06F11/3409 , G06F11/3466 , G06F11/3612 , G06F11/3636 , G06F11/3648 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： Monitoring performance of one or more architecturally significant processor caches coupled to a processor. The methods include executing an application on one or more processors coupled to one or more architecturally significant processor caches, where the application utilizes the architecturally significant portions of the architecturally significant processor caches. The methods further include at least one of generating metrics related to performance of the architecturally significant processor caches; implementing one or more debug exceptions related to performance of the architecturally significant processor caches; or implementing one or more transactional breakpoints related to performance of the architecturally significant processor caches as a result of utilizing the architecturally significant portions of the architecturally significant processor caches.
摘要翻译：监视耦合到处理器的一个或多个架构上重要的处理器高速缓存的性能。所述方法包括在耦合到一个或多个架构有意义的处理器高速缓存的一个或多个处理器上执行应用，其中应用利用架构上重要的处理器高速缓存的架构上重要的部分。所述方法还包括生成与架构上重要的处理器高速缓存的性能有关的度量中的至少一个; 实现与架构上重要的处理器高速缓存的性能相关的一个或多个调试异常; 或者通过利用架构上重要的处理器高速缓存的架构上重要的部分来实现与架构上重要的处理器高速缓存的性能相关的一个或多个事务性断点。

2. 发明授权

US08719514B2 Software filtering in a transactional memory system 有权
标题翻译：事务存储系统中的软件过滤
公开(公告)号：US08719514B2
公开(公告)日：2014-05-06
申请号：US12653471
申请日：2009-12-15
申请人： Ali-Reza Adl-Tabatabai , David Callahan , Jan Gray , Vinod Grover , Bratin Saha , Gad Sheaffer
发明人： Ali-Reza Adl-Tabatabai , David Callahan , Jan Gray , Vinod Grover , Bratin Saha , Gad Sheaffer
IPC分类号： G06F13/00
CPC分类号： G06F9/522 , G06F8/458 , G06F9/467
摘要： A method and apparatus for utilizing hardware mechanisms of a transactional memory system is herein described. Various embodiments relate to software-based filtering of operations from read and write barriers and read isolation barriers during transactional execution. Other embodiments relate to software-implemented read barrier processing to accelerate strong atomicity. Other embodiments are also described and claimed.
摘要翻译：这里描述了一种利用事务存储器系统的硬件机制的方法和装置。各种实施例涉及在事务执行期间从读写障碍和读隔离屏障的基于软件的操作过滤。其他实施例涉及软件实现的读屏障处理以加速强原子性。还描述和要求保护其他实施例。

3. 发明授权

US08688951B2 Operating system virtual memory management for hardware transactional memory 有权
标题翻译：硬件事务内存的操作系统虚拟内存管理
公开(公告)号：US08688951B2
公开(公告)日：2014-04-01
申请号：US13554558
申请日：2012-07-20
申请人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
发明人： Koichi Yamada , Gad Sheaffer , Ali-Reza Adl-Tabatabai , Landy Wang , Martin Taillefer , Arun Kishan , David Callahan , Jan Gray , Vadim Bassin
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/26 , G06F9/34 , G06F9/455 , G06F9/46
CPC分类号： G06F12/1045 , G06F12/0815
摘要： Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.
摘要翻译：硬件事务内存的操作系统虚拟内存管理。系统包括决定取消映射第一虚拟页面的操作系统。结果，操作系统从虚拟存储器页表移除第一虚拟页面到第一物理页面的映射。结果，操作系统执行至少第一物理页丢弃事务存储器硬件状态的动作。实施例可以进一步挂起内核模式下的硬件事务。实施例可以进一步执行软页错误处理，而不中止硬件事务，在返回到用户模式时恢复硬件事务，甚至成功地提交硬件事务。

4. 发明授权

US08521995B2 Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode 有权
标题翻译：以无界事务内存（UTM）模式处理操作系统（OS）转换
公开(公告)号：US08521995B2
公开(公告)日：2013-08-27
申请号：US12638064
申请日：2009-12-15
申请人： Koichi Yamada , Gad Sheaffer , Jan Gray , Landy Wang , Martin Taillefer , Arun Kishan , Ali-Reza Adl-Tabatabai , David Callahan
发明人： Koichi Yamada , Gad Sheaffer , Jan Gray , Landy Wang , Martin Taillefer , Arun Kishan , Ali-Reza Adl-Tabatabai , David Callahan
IPC分类号： G06F13/14
CPC分类号： G06F9/3834 , G06F9/30076 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3861 , G06F9/461 , G06F9/467 , G06F9/4812 , G06F2209/481
摘要： A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a transaction status register (TSR) associated with the user thread and storing the TSR with a context of the user thread, and later restoring the context during a transition from the kernel mode to the user thread. In this way, the UTM transaction may continue on resumption of the user thread.
摘要翻译：一种方法包括：在执行无界事务存储器（UTM）事务期间，通过来自用户线程的环转移接收控制，更新与用户线程相关联的事务状态寄存器（TSR）的状态并将TSR与用户线程的上下文，然后在从内核模式到用户线程的转换期间恢复上下文。以这种方式，UTM事务可以继续恢复用户线程。

5. 发明授权

US08402218B2 Efficient garbage collection and exception handling in a hardware accelerated transactional memory system 有权
标题翻译：在硬件加速事务内存系统中高效的垃圾回收和异常处理
公开(公告)号：US08402218B2
公开(公告)日：2013-03-19
申请号：US12638929
申请日：2009-12-15
申请人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
发明人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Vinod K. Grover , Michael Magruder , Gad Sheaffer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/466 , G06F9/3004 , G06F9/30087 , G06F9/30185 , G06F9/3834 , G06F9/467 , G06F12/0253 , G06F12/0815 , G06F12/082
摘要： Handling garbage collection and exceptions in hardware assisted transactions. Embodiments are practiced in a computing environment including a hardware assisted transaction system. Embodiments includes acts for writing to a card table outside of a transaction; handling garbage collection compaction occurring when a hardware transaction is active by using a common global variable and instructing one or more agents to write to the common global variable any time an operation is performed which may change an object's virtual address; acts for managing a thread-local allocation context; acts for handling exceptions while in a hardware assisted transaction. A method includes beginning a hardware assisted transaction, raising an exception while in the hardware assisted transaction, including creating an exception object, determining that the transaction should be rolled back, and as a result of determining that the transaction should be rolled back, marshaling the exception object out of the hardware assisted transaction.
摘要翻译：在硬件辅助交易中处理垃圾收集和异常。实施例在包括硬件辅助交易系统的计算环境中实现。实施例包括用于在事务之外写入卡表的动作; 通过使用公共全局变量来处理在硬件事务处于活动状态时发生的垃圾收集压缩，并且在每次执行可能改变对象的虚拟地址的操作时，指示一个或多个代理写入公共全局变量; 用于管理线程本地分配上下文的动作; 在硬件辅助交易中处理异常的行为。一种方法包括开始硬件辅助事务，在硬件辅助事务中引发异常，包括创建异常对象，确定事务应该回滚，并且由于确定事务应该回滚，因此，异常对象出来的硬件辅助事务。

6. 发明授权

US08356166B2 Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers 有权
标题翻译：通过使用模式不可知事务读写障碍来最大限度地减少无界事务内存系统中的代码重复
公开(公告)号：US08356166B2
公开(公告)日：2013-01-15
申请号：US12493168
申请日：2009-06-26
申请人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
发明人： Ali-Reza Adl-Tabatabai , Bratin Saha , Gad Sheaffer , Vadim Bassin , Robert Y. Geva , Martin Taillefer , Darek Mihocka , Burton Jordan Smith , Jan Gray
IPC分类号： G06F15/00 , G06F9/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/3004 , G06F9/30076 , G06F9/30087 , G06F9/30101 , G06F9/30181 , G06F9/30189 , G06F9/3857 , G06F9/467
摘要： Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.
摘要翻译：最大限度地减少无界事务内存系统中的代码重复。一种包括一个或多个处理器的计算设备，其中可以使用在传统ISA和扩展ISA处理器上运行的一组共同模式不可知TM屏障序列，并且采用硬件滤波器指示器（当可用时）可以过滤冗余应用 TM屏障，并且使得主体代码的编译二进制表示可以在任何当前实现的事务存储器执行模式集中运行，包括在事务之外运行代码，并且使得相同的编译的二进制文件能够继续工作与未来的TM实现可能会引入未知的未来TM执行模式。

7. 发明申请

US20110145798A1 DEBUGGING MECHANISMS IN A CACHE-BASED MEMORY ISOLATION SYSTEM 有权
标题翻译：基于缓存的内存分离系统中的调试机制
公开(公告)号：US20110145798A1
公开(公告)日：2011-06-16
申请号：US12646438
申请日：2009-12-23
申请人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
发明人： Martin Taillefer , Ali-Reza Adl-Tabatabai , Gad Sheaffer , Peter Lachner , Richard Wurdack , Darek Mihocka , Jan Gray
IPC分类号： G06F9/44 , G06F15/76
CPC分类号： G06F11/362 , G06F12/0817
摘要： Debugging software in systems with architecturally significant processor caches. A method may be practiced in a computing environment. The method includes acts for debugging a software application, wherein the software application is configured to use one or more architecturally significant processor caches coupled to a processor. The method includes beginning execution of the software application. A debugger is run while executing the software application. The software application causes at least one of reads or writes to be made to the cache in an architecturally significant fashion. The reads or writes made to the cache in an architecturally significant fashion are preserved while performing debugging operations that would ordinarily disturb the reads or writes made to the cache in an architecturally significant fashion.
摘要翻译：在具有架构上重要的处理器高速缓存的系统中调试软件。可以在计算环境中实施一种方法。该方法包括用于调试软件应用程序的动作，其中软件应用被配置为使用耦合到处理器的一个或多个架构上重要的处理器高速缓存。该方法包括开始执行软件应用程序。在执行软件应用程序时运行调试器。软件应用程序使得以架构上显着的方式对缓存进行读取或写入中的至少一个。以架构上显着的方式对高速缓存进行的读取或写入被保留，同时执行调整操作，这些调试操作通常会以建筑上重要的方式干扰对高速缓存的读取或写入。

8. 发明申请

US20100332771A1 PRIVATE MEMORY REGIONS AND COHERENCE OPTIMIZATIONS 有权
标题翻译：私人存储区域和协调优化
公开(公告)号：US20100332771A1
公开(公告)日：2010-12-30
申请号：US12493164
申请日：2009-06-26
申请人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
发明人： Jan Gray , David Callahan , Burton Jordan Smith , Gad Sheaffer , Ali-Reza Adl-Tabatabai
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F9/467 , G06F12/0811 , G06F12/0831 , G06F2209/521
摘要： Private or shared read-only memory regions. One embodiment may be practiced in a computing environment including a plurality of agents. A method includes acts for declaring one or more memory regions private to a particular agent or shared read only amongst agents by having software utilize processor level instructions to specify to hardware the private or shared read only memory address regions. The method includes an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents. As a result of an agent executing a processor level instruction to specify one or more memory regions as private to the agent or shared read-only amongst a plurality of agents, a hardware component monitoring the one or more memory regions for conflicting accesses or prevents conflicting accesses on the one or more memory regions.
摘要翻译：专用或共享只读存储器区域。一个实施例可以在包括多个代理的计算环境中实践。一种方法包括通过使软件利用处理器级指令向硬件指定私有或共享的只读存储器地址区域来将用于声明特定代理私有的一个或多个存储器区域或仅在代理之间共享的操作。该方法包括执行处理器级别指令的代理，以指定对代理私有的一个或多个存储器区域或者在多个代理之间共享只读。作为代理执行处理器级别指令的结果，所述处理器级指令指定一个或多个存储器区域对于所述代理是专用的，或者在多个代理之间共享为只读存储器区域，硬件组件监视所述一个或多个存储器区域以进行冲突访问或防止冲突访问一个或多个存储器区域。

9. 发明申请

US20100332538A1 HARDWARE ACCELERATED TRANSACTIONAL MEMORY SYSTEM WITH OPEN NESTED TRANSACTIONS 有权
标题翻译：具有开放式交易的硬件加速交易记忆系统
公开(公告)号：US20100332538A1
公开(公告)日：2010-12-30
申请号：US12495582
申请日：2009-06-30
申请人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Michael Magruder , David Callahan
发明人： Jan Gray , Martin Taillefer , Yosseff Levanoni , Ali-Reza Adl-Tabatabai , Dave Detlefs , Michael Magruder , David Callahan
IPC分类号： G06F17/30
CPC分类号： G06F17/30377
摘要： Hardware assisted transactional memory system with open nested transactions. Some embodiments described herein implement a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.
摘要翻译：具有开放嵌套交易的硬件辅助事务内存系统。这里描述的一些实施例实现了一种系统，其中可以通过在硬件中实现开放式嵌套事务来实现事务的硬件加速，这些交易涉及软件锁定，使得顶级事务可以以软件实现，并且因此不受硬件约束的限制事务性存储系统。

10. 发明授权

US07222217B2 Cache residency test instruction 有权
标题翻译：缓存驻留测试指令
公开(公告)号：US07222217B2
公开(公告)日：2007-05-22
申请号：US10609105
申请日：2003-06-27
申请人： Jan Gray
发明人： Jan Gray
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F9/30047 , G06F12/0802
摘要： A cache residency test instruction is described which, when executed by a processor unit, allows the processor unit to determine if a set of data resides in a cache memory that is communicatively coupled to the processor unit and communicate a result of the determination to software being executed on the processor unit.
摘要翻译：描述了缓存驻留测试指令，当由处理器单元执行时，该处理器单元允许处理器单元确定一组数据是否驻留在通信地耦合到处理器单元的高速缓冲存储器中，并将确定的结果传达给软件在处理器单元上执行。

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