专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06251746B1 Methods of forming trench isolation regions having stress-reducing nitride layers therein 失效
标题翻译：在其中形成具有应力减小氮化物层的沟槽隔离区的方法
公开(公告)号：US06251746B1
公开(公告)日：2001-06-26
申请号：US09415475
申请日：1999-10-08
申请人： Soo-Jin Hong , Yung-Seob Yu , Bon-Young Koo , Byung-Ki Kim , Seung-Mok Shin
发明人： Soo-Jin Hong , Yung-Seob Yu , Bon-Young Koo , Byung-Ki Kim , Seung-Mok Shin
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.
摘要翻译：形成沟槽隔离区的方法包括以下步骤：使用沟槽掩模层作为蚀刻掩模，在半导体衬底上形成包含第一材料（例如多晶硅）的沟槽屏蔽层，然后蚀刻半导体衬底中的沟槽。然后在沟槽的侧壁和沟槽掩模层的侧壁上形成包括不同于第一材料的第二材料的沟槽氮化物层。然后用沟槽绝缘材料（例如USG）填充沟槽。然后通过用比第二材料更高的速率选择性地蚀刻第一材料的蚀刻剂选择性蚀刻沟槽掩模层来去除沟槽掩模层。去除沟槽屏蔽层的这个步骤导致了沟槽氮化物层的突出部分的曝光，但是不会使沟槽氮化物层变凹陷。然后将沟槽绝缘材料和沟槽氮化物层回蚀刻以限定沟槽隔离区域。

2. 发明授权

US09368495B2 Semiconductor devices having bridge layer and methods of manufacturing the same 有权
标题翻译：具有桥接层的半导体器件及其制造方法
公开(公告)号：US09368495B2
公开(公告)日：2016-06-14
申请号：US14576368
申请日：2014-12-19
申请人： Seok-Hoon Kim , Jin-Bum Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Jin-Hee Han , Bon-Young Koo
发明人： Seok-Hoon Kim , Jin-Bum Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Jin-Hee Han , Bon-Young Koo
IPC分类号： H01L21/00 , H01L27/088 , H01L27/02 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475 , H01L27/0207 , H01L27/0924 , H01L27/1104 , H01L29/0649 , H01L29/41791 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785
摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
摘要翻译：半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层，多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

3. 发明申请

US20110045647A1 METHODS OF FORMING NON-VOLATILE MEMORY DEVICES 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US20110045647A1
公开(公告)日：2011-02-24
申请号：US12916718
申请日：2010-11-01
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

4. 发明申请

US20070228911A1 Refrigerator 审中-公开
标题翻译：冰箱
公开(公告)号：US20070228911A1
公开(公告)日：2007-10-04
申请号：US11730538
申请日：2007-04-02
申请人： Jong-Gon Kim , Oh-Chul Kwon , Yoo-Min Park , Young-Hoon Gwak , Hyeon-Po Cho , Bon-Young Koo , Myung-Soo Kim , Suk-Hyoun Cho
发明人： Jong-Gon Kim , Oh-Chul Kwon , Yoo-Min Park , Young-Hoon Gwak , Hyeon-Po Cho , Bon-Young Koo , Myung-Soo Kim , Suk-Hyoun Cho
IPC分类号： A47B96/04
CPC分类号： F25D23/067 , F25D23/064
摘要： A refrigerator comprises: an inner case that forms a storage space; a plurality of fixing members coupled to the inner case so as to be protruding to the storage space, for preventing a foaming agent applied to a rear surface of the inner case from leaking to the storage space; and a guide rail fixedly-coupled to the fixing members, and to which a storage means is slidably coupled. Since components for slidably coupling a storage means to the inner case are simplified and an assembly process is facilitated, a production cost is reduced and a productivity is enhanced. Furthermore, the components for slidably coupling the storage means to the inner case are firmly coupled to the inner case, and a foaming agent is prevented from leaking to inside of the inner case, thereby enhancing the reliability of the product.
摘要翻译：冰箱包括：形成存储空间的内壳; 多个固定构件，其联接到所述内壳体以便突出到所述存储空间，用于防止施加到所述内壳体的后表面的发泡剂泄漏到所述存储空间; 以及固定地连接到固定构件的导轨，并且存储装置可滑动地连接在该导轨上。由于用于将存储装置可滑动地联接到内壳的部件被简化并且容易组装过程，因此降低了生产成本并提高了生产率。此外，用于将存储装置可滑动地联接到内壳的部件牢固地联接到内壳，并且防止发泡剂泄漏到内壳的内部，从而增强了产品的可靠性。

5. 发明申请

US20070167030A1 Method of forming an insulation structure and method of manufacturing a semiconductor device using the same 有权
标题翻译：绝缘结构的形成方法及其制造方法
公开(公告)号：US20070167030A1
公开(公告)日：2007-07-19
申请号：US11639164
申请日：2006-12-15
申请人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
发明人： Jung-Geun Jee , Young-Jin Noh , Bon-Young Koo , Chul-Sung Kim , Hun-Hyeoung Leam , Woong Lee
IPC分类号： H01L21/31
CPC分类号： H01L21/3144 , H01L21/0217 , H01L21/022 , H01L21/02238 , H01L21/02252 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/31662 , H01L27/115 , H01L27/11521
摘要： In a method of forming an insulation structure, at least one oxide layer is formed on an object by at least one oxidation process, and then at least one nitride layer is formed from the oxide layer by at least one nitration process. An edge portion of the insulation structure may have a thickness substantially the same as that of a central portion of the insulation structure so that the insulation structure may have a uniform thickness and improved insulation characteristics. When the insulation structure is employed as a tunnel insulation layer of a semiconductor device, the semiconductor device may have enhanced endurance and improved electrical characteristics because a threshold voltage distribution of cells in the semiconductor device may become uniform.
摘要翻译：在形成绝缘结构的方法中，通过至少一个氧化工艺在物体上形成至少一个氧化物层，然后通过至少一个硝化工艺从氧化物层形成至少一个氮化物层。绝缘结构的边缘部分可以具有与绝缘结构的中心部分的厚度基本相同的厚度，使得绝缘结构可以具有均匀的厚度和改善的绝缘特性。当采用绝缘结构作为半导体器件的隧道绝缘层时，由于半导体器件中的单元的阈值电压分布可能变得均匀，所以半导体器件可以具有增强的耐久性和改善的电特性。

6. 发明授权

US07218942B2 Method for transmitting digital channel with priority of mobile communication terminal 有权
标题翻译：用于发送移动通信终端优先级的数字信道的方法
公开(公告)号：US07218942B2
公开(公告)日：2007-05-15
申请号：US10641152
申请日：2003-08-15
申请人： Bon-Young Koo , Young-Shim Kim
发明人： Bon-Young Koo , Young-Shim Kim
IPC分类号： H04Q7/20
CPC分类号： H04W48/16 , H04W76/10 , H04W88/06 , H04W88/10
摘要： A method for transmitting a call signal through a digital channel while in an analog area is provided which allows for enhanced speech and transmission quality while in the analog area. When a call is originated in an analog area, a mobile communication terminal scans a most recently used (MRU) table to locate a digital channel which matches a digital channel available in the analog area. If there is a match, the call is placed through the available digital channel. If none of the digital channels in the MRU table matches the available digital channel, then the call is placed through an analog channel.
摘要翻译：提供一种用于在模拟区域中通过数字通道发送呼叫信号的方法，其允许在模拟区域中增强语音和传输质量。当呼叫发生在模拟区域时，移动通信终端扫描最近使用的（MRU）表以定位与模拟区域中可用的数字信道相匹配的数字信道。如果有匹配，则通过可用的数字频道进行呼叫。如果MRU表中的数字通道都不匹配可用的数字通道，则通过模拟通道进行通话。

7. 发明申请

US20050285162A1 Semiconductor devices having a stacked structure and methods of forming the same 审中-公开
标题翻译：具有堆叠结构的半导体器件及其形成方法
公开(公告)号：US20050285162A1
公开(公告)日：2005-12-29
申请号：US11159596
申请日：2005-06-23
申请人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
发明人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
IPC分类号： H01L21/8244 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.
摘要翻译：形成具有堆叠结构的半导体器件的方法包括在衬底上形成第一半导体结构并在衬底上形成第一层间绝缘层。第一层间绝缘层具有基本上平坦的上表面。在第一层间绝缘层上形成半导体层，在半导体层上形成第一栅极绝缘层，该处理温度被选择为控制第一半导体结构的损坏。在第一栅绝缘层上形成第二半导体结构。

8. 发明授权

US06930062B2 Methods of forming an oxide layer in a transistor having a recessed gate 失效
标题翻译：在具有凹入栅极的晶体管中形成氧化物层的方法
公开(公告)号：US06930062B2
公开(公告)日：2005-08-16
申请号：US10850690
申请日：2004-05-21
申请人： Sang-Jin Hyun , Yu-Gyun Shin , Bon-Young Koo , Sug-Hun Hong , Taek-Soo Jeon , Jeong-do Ryu
发明人： Sang-Jin Hyun , Yu-Gyun Shin , Bon-Young Koo , Sug-Hun Hong , Taek-Soo Jeon , Jeong-do Ryu
IPC分类号： H01L21/336 , H01L21/316 , H01L21/762 , H01L21/26
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/31662 , H01L21/76235
摘要： A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
摘要翻译：在半导体衬底上形成氧化物层的方法包括热氧化衬底的表面以在衬底上形成氧化物层，然后将氧化物层暴露于主要包含氧自由基的环境，从而使氧化物层变厚。还讨论了制造凹陷栅极晶体管的相关方法。

9. 发明授权

US09972716B2 Semiconductor devices 有权
公开(公告)号：US09972716B2
公开(公告)日：2018-05-15
申请号：US14826439
申请日：2015-08-14
申请人： Jin-Bum Kim , Seok-Hoon Kim , Chul Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Su-Jin Jung , Bon-Young Koo
发明人： Jin-Bum Kim , Seok-Hoon Kim , Chul Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Su-Jin Jung , Bon-Young Koo
IPC分类号： H01L29/78 , H01L29/06 , H01L29/32 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/3221 , H01L29/165 , H01L29/32 , H01L29/66545 , H01L29/66636 , H01L29/785
摘要： Provided are semiconductor devices that include an active pattern on a substrate, first and second gate electrodes on the active pattern and arranged in a first direction relative to one another and a first source/drain region in a first trench that extends into the active pattern between the first and second gate electrodes. The first source/drain region includes a first epitaxial layer that is configured to fill the first trench and that includes at least one plane defect that originates at a top portion of the first epitaxial layer and extends towards a bottom portion of the first epitaxial layer.

10. 发明授权

US09595611B2 FinFET with a single contact to multiple fins bridged together to form a source/drain region of the transistor 有权
标题翻译： FinFET具有与多个鳍片的单个接触，桥接在一起以形成晶体管的源极/漏极区域
公开(公告)号：US09595611B2
公开(公告)日：2017-03-14
申请号：US14262712
申请日：2014-04-26
申请人： Seok-Hoon Kim , Bon-Young Koo , Nam-Kyu Kim , Woo-Bin Song , Byeong-Chan Lee , Su-Jin Jung
发明人： Seok-Hoon Kim , Bon-Young Koo , Nam-Kyu Kim , Woo-Bin Song , Byeong-Chan Lee , Su-Jin Jung
IPC分类号： H01L29/78 , H01L21/8234 , H01L29/66 , H01L27/12
CPC分类号： H01L29/785 , H01L21/823431 , H01L27/0886 , H01L27/1211 , H01L29/0847 , H01L29/66545 , H01L29/66795 , H01L29/6681
摘要： A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.
摘要翻译：半导体器件可以包括在衬底上并排形成的第一和第二鳍片，形成在第一鳍片上并具有杂质的第一掺杂浓度的第一升高掺杂区域，形成在第二鳍片上的第二高掺杂区域，将第一升高掺杂区域和第二升高掺杂区域彼此连接的桥。还公开了制造这种半导体器件的方法。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式