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1. 发明申请

US20110045647A1 METHODS OF FORMING NON-VOLATILE MEMORY DEVICES 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US20110045647A1
公开(公告)日：2011-02-24
申请号：US12916718
申请日：2010-11-01
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

2. 发明授权

US08525275B2 Methods of forming non-volatile memory devices 有权
标题翻译：形成非易失性存储器件的方法
公开(公告)号：US08525275B2
公开(公告)日：2013-09-03
申请号：US12916718
申请日：2010-11-01
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L21/28282 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

3. 发明申请

US20090020805A1 NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US20090020805A1
公开(公告)日：2009-01-22
申请号：US11950143
申请日：2007-12-04
申请人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
发明人： Jin-Hwa Heo , Chul-Sung Kim , Bon-Young Koo , Ki-Hyun Hwang , Chang-Hyun Lee
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/792 , H01L21/28202 , H01L29/40117 , H01L29/4234 , H01L29/513 , H01L29/518
摘要： A non-volatile memory device includes a dielectric layer between a charge storage layer and a substrate. Free bonds of the dielectric layer can be reduced to reduce/prevent charges from leaking through the free bonds and/or from being trapped by the free bonds. As a result, data retention properties and/or durability of a non-volatile memory device may be enhanced.
摘要翻译：非易失性存储器件包括电荷存储层和衬底之间的电介质层。可以减少电介质层的自由键，以减少/防止电荷通过游离键泄漏和/或被游离键捕获。结果，可以增强非挥发性存储器件的数据保持性能和/或耐久性。

4. 发明授权

US08008154B2 Methods of forming impurity containing insulating films and flash memory devices including the same 失效
标题翻译：形成含杂质的绝缘膜的方法和包括其的闪存器件的方法
公开(公告)号：US08008154B2
公开(公告)日：2011-08-30
申请号：US12188482
申请日：2008-08-08
申请人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
发明人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
IPC分类号： H01L21/336
CPC分类号： H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.
摘要翻译：形成绝缘膜的方法包括在基板上形成绝缘膜。使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

5. 发明申请

US20090130834A1 METHODS OF FORMING IMPURITY CONTAINING INSULATING FILMS AND FLASH MEMORY DEVICES INCLUDING THE SAME 失效
标题翻译：形成包含绝缘膜的绝缘体的方法和包括其的闪存存储器件
公开(公告)号：US20090130834A1
公开(公告)日：2009-05-21
申请号：US12188482
申请日：2008-08-08
申请人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
发明人： Young-Jin Noh , Bon-Young Koo , Si-Young Choi , Ki-Hyun Hwang , Chul-Sung Kim , Sung-Kweon Baek , Jin-Hwa Heo
IPC分类号： H01L21/4763 , H01L21/469
CPC分类号： H01L29/42324 , H01L21/0214 , H01L21/02238 , H01L21/02255 , H01L21/02332 , H01L21/02337 , H01L21/28273 , H01L21/3145 , H01L21/31662
摘要： Methods of forming an insulating film include forming an insulating film on a substrate. A first impurity is injected into the insulating film using a thermal process under a first set of processing conditions to form a first impurity concentration peak in a lower portion of the insulating film. A second impurity is injected into the insulating film using the thermal process under a second set of processing conditions, different from the first set of processing conditions, to form a second impurity concentration peak in an upper portion of the insulating film. Injecting the first impurity and injecting the second impurity may be carried out without using plasma and the first impurity concentration peak may be higher than the second impurity concentration peak.
摘要翻译：形成绝缘膜的方法包括在基板上形成绝缘膜。使用第一组处理条件下的热处理将第一杂质注入绝缘膜，以在绝缘膜的下部形成第一杂质浓度峰。在与第一组处理条件不同的第二组处理条件下，使用热处理将第二杂质注入到绝缘膜中，以在绝缘膜的上部形成第二杂质浓度峰。注入第一杂质并注入第二杂质可以在不使用等离子体的情况下进行，并且第一杂质浓度峰可以高于第二杂质浓度峰。

6. 发明申请

US20050285162A1 Semiconductor devices having a stacked structure and methods of forming the same 审中-公开
标题翻译：具有堆叠结构的半导体器件及其形成方法
公开(公告)号：US20050285162A1
公开(公告)日：2005-12-29
申请号：US11159596
申请日：2005-06-23
申请人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
发明人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
IPC分类号： H01L21/8244 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.
摘要翻译：形成具有堆叠结构的半导体器件的方法包括在衬底上形成第一半导体结构并在衬底上形成第一层间绝缘层。第一层间绝缘层具有基本上平坦的上表面。在第一层间绝缘层上形成半导体层，在半导体层上形成第一栅极绝缘层，该处理温度被选择为控制第一半导体结构的损坏。在第一栅绝缘层上形成第二半导体结构。

7. 发明申请

US20080085584A1 OXIDATION/HEAT TREATMENT METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的氧化/热处理方法
公开(公告)号：US20080085584A1
公开(公告)日：2008-04-10
申请号：US11857824
申请日：2007-09-19
申请人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
发明人： Young-Jin Noh , Chul-Sung Kim , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang , Sung-Kweon Baek
IPC分类号： H01L21/336
CPC分类号： H01L21/28247 , H01L29/40114
摘要： Methods of manufacturing non-volatile memory devices are disclosed which may at least partially cure etch damage and may at least partially remove defect sites in gate structures of the devices caused during manufacturing of the devices. An exemplary method of manufacturing a non-volatile memory device includes forming a gate structure on a substrate, the gate structure including a control gate electrode, a blocking layer pattern, a floating gate electrode, and a tunnel insulating layer pattern. An oxidation process is performed that at least partially cures damage caused to the substrate and to the gate structure during formation of the gate structure. A first heat treatment is performed under a gas atmosphere including nitrogen to at least partially remove defect sites on the gate structure caused by the oxidation process. A second heat treatment is performed under a gas atmosphere including chlorine to at least partially remove remaining defect sites on the gate structure caused by the oxidation process.
摘要翻译：公开了制造非易失性存储器件的方法，其可以至少部分地固化蚀刻损伤，并且可以至少部分地去除在器件的制造期间引起的器件的栅极结构中的缺陷位置。制造非易失性存储器件的示例性方法包括在衬底上形成栅极结构，栅极结构包括控制栅电极，阻挡层图案，浮栅电极和隧道绝缘层图案。进行氧化处理，其至少部分地固化在栅极结构形成期间对衬底和栅极结构的损伤。在包括氮气的气体气氛下进行第一热处理，以至少部分地去除由氧化过程引起的栅极结构上的缺陷部位。在包括氯的气体气氛下进行第二热处理，以至少部分地去除由氧化过程引起的栅极结构上的剩余缺陷部位。

8. 发明授权

US06214688B1 Methods of forming integrated circuit capacitors having U-shaped electrodes 有权
标题翻译：形成具有U形电极的集成电路电容器的方法
公开(公告)号：US06214688B1
公开(公告)日：2001-04-10
申请号：US09289347
申请日：1999-04-09
申请人： Ki-Hyun Hwang , Chang-Won Choi , Seok-Woo Nam , Bon-Young Koo
发明人： Ki-Hyun Hwang , Chang-Won Choi , Seok-Woo Nam , Bon-Young Koo
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode.
摘要翻译：形成集成电路电容器的方法包括在半导体衬底上形成其中具有导电插塞的第一电绝缘层，然后在第一电绝缘层上形成不同材料的第二和第三电绝缘层的步骤。然后形成接触孔以延伸穿过第二和第三电绝缘层并暴露导电插塞。接下来，在接触孔和第三电绝缘层中形成导电层。然后进行步骤以平坦化导电层以在接触孔中限定U形电极。然后使用第二电绝缘层作为蚀刻停止层，蚀刻回第三电绝缘层以暴露U形电极的外侧壁的上部。然而，第二电绝缘层不被去除，而是作为U形电极的支撑层。该第二电绝缘层优选地包括氮化物层和氧化物层的复合物。为了增加U形电极的有效表面积，也可以在U形电极的内侧壁和外侧壁上形成HSG层。

9. 发明申请

US20090072294A1 Method of manufacturing a non-volatile memory device 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090072294A1
公开(公告)日：2009-03-19
申请号：US11974636
申请日：2007-10-15
申请人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
发明人： Sang-Ryol Yang , Sung-Kweon Baek , Si-Young Choi , Bon-Young Koo , Ki-Hyun Hwang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method of manufacturing a non-volatile memory device employing a relatively thin polysilicon layer as a floating gate is disclosed, wherein a tunnel oxide layer is formed on a substrate and a polysilicon layer having a thickness of about 35 Å to about 200 Å is then formed on the tunnel oxide layer using a trisilane (Si3H8) gas as a silicon source gas. The tunnel oxide layer and the polysilicon layer are then patterned into a tunnel oxide layer pattern and a polysilicon layer pattern, respectively. A dielectric layer and a conductive layer corresponding to a control gate are subsequently formed on the polysilicon layer pattern. The polysilicon layer is formed using trisilane (Si3H8) gas as a result of which the polysilicon layer may be formed to have a relatively thin thickness while maintaining a thickness uniformity and realizing a superior morphology thus producing a floating gate having enhanced performance.
摘要翻译：公开了一种使用相对薄的多晶硅层作为浮动栅极的非易失性存储器件的制造方法，其中在衬底上形成隧道氧化物层，然后形成厚度为约至大约的厚度的多晶硅层使用丙硅烷（Si 3 H 8）气体作为硅源气体在隧道氧化物层上形成。然后将隧道氧化物层和多晶硅层分别图案化为隧道氧化物层图案和多晶硅层图案。随后在多晶硅层图案上形成对应于控制栅的电介质层和导电层。使用丙硅烷（Si 3 H 8）气体形成多晶硅层，结果可以形成多晶硅层以具有相对较薄的厚度，同时保持厚度均匀性并实现优异的形态，从而产生具有增强性能的浮栅。

10. 发明授权

US06838719B2 Dram cell capacitors having U-shaped electrodes with rough inner and outer surfaces 有权
标题翻译：具有内表面和内表面粗糙的U形电极的电容器电容器
公开(公告)号：US06838719B2
公开(公告)日：2005-01-04
申请号：US10223751
申请日：2002-08-20
申请人： Ki-Hyun Hwang , Chang-Won Choi , Seok-Woo Nam , Bon-Young Koo , Young-Sub Yu , Han-Jin Lim
发明人： Ki-Hyun Hwang , Chang-Won Choi , Seok-Woo Nam , Bon-Young Koo , Young-Sub Yu , Han-Jin Lim
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10852 , H01L28/84
摘要： Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode.

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