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1. 发明授权

US09397219B2 Semiconductor devices having source/drain regions with strain-inducing layers and methods of manufacturing such semiconductor devices 有权
标题翻译：具有应变诱导层的源极/漏极区域的半导体器件以及制造这种半导体器件的方法
公开(公告)号：US09397219B2
公开(公告)日：2016-07-19
申请号：US14680458
申请日：2015-04-07
申请人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
发明人： Seok-hoon Kim , Jin-bum Kim , Kwan-heum Lee , Byeong-chan Lee , Cho-eun Lee , Su-jin Jung
IPC分类号： H01L21/302 , H01L21/461 , H01L29/78 , H01L29/165
CPC分类号： H01L29/7848 , H01L21/02236 , H01L21/02255 , H01L21/02532 , H01L21/02636 , H01L21/823431 , H01L21/823821 , H01L27/0886 , H01L27/0924 , H01L29/0649 , H01L29/1033 , H01L29/1054 , H01L29/165 , H01L29/41791 , H01L29/66795 , H01L29/7831 , H01L29/785 , H01L29/7851 , H01L29/7856
摘要： Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in the device, and a method of manufacturing the device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region. The gate structure includes a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.
摘要翻译：半导体器件包括能够对包括在器件中的晶体管的沟道区域施加应变的应变诱导层以及该器件的制造方法。半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并且沿着第一方向布置在所述沟道区的两侧; 以及设置在通道区域上的栅极结构。栅极结构包括沿与第一方向不同的第二方向延伸的栅极电极图案，沟道区域和栅电极图案之间的栅极介电层以及覆盖栅电极图案的各个侧表面的栅极间隔栅介质层。源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

2. 发明授权

US09368495B2 Semiconductor devices having bridge layer and methods of manufacturing the same 有权
标题翻译：具有桥接层的半导体器件及其制造方法
公开(公告)号：US09368495B2
公开(公告)日：2016-06-14
申请号：US14576368
申请日：2014-12-19
申请人： Seok-Hoon Kim , Jin-Bum Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Jin-Hee Han , Bon-Young Koo
发明人： Seok-Hoon Kim , Jin-Bum Kim , Kwan-Heum Lee , Byeong-Chan Lee , Cho-Eun Lee , Jin-Hee Han , Bon-Young Koo
IPC分类号： H01L21/00 , H01L27/088 , H01L27/02 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475 , H01L27/0207 , H01L27/0924 , H01L27/1104 , H01L29/0649 , H01L29/41791 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785
摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
摘要翻译：半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层，多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

3. 发明申请

US20150333061A1 SEMICONDUCTOR DEVICES HAVING BRIDGE LAYER AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：具有桥接层的半导体器件及其制造方法
公开(公告)号：US20150333061A1
公开(公告)日：2015-11-19
申请号：US14576368
申请日：2014-12-19
申请人： Seok-Hoon KIM , Jin-Bum KIM , Kwan-Heum LEE , Byeong-Chan LEE , Cho-Eun LEE , Jin-Hee HAN , Bon-Young KOO
发明人： Seok-Hoon KIM , Jin-Bum KIM , Kwan-Heum LEE , Byeong-Chan LEE , Cho-Eun LEE , Jin-Hee HAN , Bon-Young KOO
IPC分类号： H01L27/088 , H01L29/78 , H01L27/02
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823475 , H01L27/0207 , H01L27/0924 , H01L27/1104 , H01L29/0649 , H01L29/41791 , H01L29/78 , H01L29/7842 , H01L29/7849 , H01L29/785
摘要： A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers on the first active fin and on the second active fin, respectively, a plurality of second epitaxial layers on the plurality of first epitaxial layers, a bridge layer connecting the plurality of second epitaxial layers to each other, and a third epitaxial layer on the bridge layer.
摘要翻译：半导体器件分别在衬底上包括衬底，第一有源鳍片和第二有源鳍片，分别在第一有源鳍片和第二有源鳍片上的多个第一外延层，多个第二外延层，多个第一外延层，将多个第二外延层彼此连接的桥接层以及桥接层上的第三外延层。

4. 发明授权

US08273620B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US08273620B2
公开(公告)日：2012-09-25
申请号：US12793809
申请日：2010-06-04
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L21/8234
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

5. 发明申请

US20110177671A1 METHODS OF FORMING A SEMICONDUCTOR CELL ARRAY REGION, METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR CELL ARRAY REGION, AND METHOD OF FORMING A SEMICONDUCTOR MODULE INCLUDING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体单元阵列区域的方法，形成包括半导体单元阵列区域的半导体器件的方法以及形成包括半导体器件的半导体器件的方法
公开(公告)号：US20110177671A1
公开(公告)日：2011-07-21
申请号：US12958858
申请日：2010-12-02
申请人： Sung-Woo HYUN , Byeong-Chan LEE , Sun-Ghil LEE , Yong-Hoon SON
发明人： Sung-Woo HYUN , Byeong-Chan LEE , Sun-Ghil LEE , Yong-Hoon SON
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L27/1052 , H01L27/10876
摘要： Methods of forming a semiconductor cell array region, a method of forming a semiconductor device including the semiconductor cell array region, and a method of forming a semiconductor module including the semiconductor device are provided, the methods of forming the semiconductor cell array region include preparing a semiconductor plate. A semiconductor layer may be formed over the semiconductor plate. The semiconductor layer may be etched to form semiconductor pillars over the semiconductor plate.
摘要翻译：提供形成半导体单元阵列区域的方法，形成包括半导体单元阵列区域的半导体器件的方法以及形成包括该半导体器件的半导体模块的方法，形成半导体单元阵列区域的方法包括：半导体板。半导体层可以形成在半导体板上。可以蚀刻半导体层以在半导体板上形成半导体柱。

6. 发明授权

US07816735B2 Integrated circuit devices including a transcription-preventing pattern 失效
标题翻译：集成电路装置，包括转录阻止图案
公开(公告)号：US07816735B2
公开(公告)日：2010-10-19
申请号：US11974293
申请日：2007-10-12
申请人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
发明人： Pil-Kyu Kang , Yong-Hoon Son , Si-Young Choi , Jong-Wook Lee , Byeong-Chan Lee , InSoo Jung
IPC分类号： H01L33/16
CPC分类号： H01L21/823425 , H01L21/823475
摘要： Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer.
摘要翻译：在第一单晶层上提供包括第一单晶层和绝缘层图案的集成电路器件。绝缘层图案在其中具有部分地暴露第一单晶层的开口。种子层在开口处。第二单晶层位于绝缘层图案和籽晶层上。第二单晶层具有与种子层基本相同的晶体结构。转录阻止图案位于转录阻止图案和第二单晶层上的第二单晶层和第三单晶层上。转录阻止图案被配置为将第二单晶层中的缺陷部分的转录限制为第三单晶层。

7. 发明授权

US07755133B2 Semiconductor integrated circuit device and related fabrication method 有权
标题翻译：半导体集成电路器件及相关制造方法
公开(公告)号：US07755133B2
公开(公告)日：2010-07-13
申请号：US11855529
申请日：2007-09-14
申请人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
发明人： Jin-bum Kim , Young-pil Kim , Si-young Choi , Byeong-chan Lee , Jong-wook Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/823418 , H01L21/823456 , H01L27/105 , H01L27/1052
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。半导体器件包括具有单元区域和周边区域的半导体衬底，形成在单元区域中的单元有源区域和形成在周边区域中的外围有源区域，其中，电池有源区域和外围有源区域由隔离区。半导体器件还包括形成在单元有源区上的第一栅极堆叠，形成在外围有源区上的第二栅极堆叠，形成在电池有源区域的暴露部分上的电池外延层和形成在电池有源区上的外围外延层所述周边有源区的暴露部分，其中所述外围外延层的高度大于所述电池外延层的高度。

8. 发明授权

US07683405B2 MOS transistors having recesses with elevated source/drain regions 有权
标题翻译： MOS晶体管具有具有升高的源极/漏极区域的凹陷
公开(公告)号：US07683405B2
公开(公告)日：2010-03-23
申请号：US10886167
申请日：2004-07-07
申请人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
发明人： Yong-Hoon Son , Si-Young Choi , Byeong-Chan Lee , Deok-Hyung Lee , In-Soo Jung
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66636 , H01L29/7833
摘要： Metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions and methods of fabricating the same are provided. The MOS transistors may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
摘要翻译：提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管及其制造方法。 MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。凹陷区域设置在与栅极图案相邻的衬底中。外凹层设置在凹陷区域的底表面上。在外延层中设置高浓度杂质区。凹陷区域可以使用化学干蚀刻技术形成。

9. 发明申请

US20090142892A1 Method of fabricating semiconductor device having thin strained relaxation buffer pattern and related device 审中-公开
标题翻译：制造具有薄应变松弛缓冲图案的半导体器件及其相关器件的方法
公开(公告)号：US20090142892A1
公开(公告)日：2009-06-04
申请号：US11984538
申请日：2007-11-19
申请人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
发明人： Byeong-Chan Lee , Si-Young Choi , Yong-Hoon Son , In-Soo Jung , Min-Gu Kang , Pil-Kyu Kang
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L21/823807 , H01L21/28052 , H01L21/823892 , H01L29/1054 , H01L29/4933 , H01L29/517
摘要： A method of fabricating a semiconductor device includes forming a buffer pattern on a substrate, the buffer pattern including germanium, recrystallizing the buffer pattern to form a strained relaxation buffer pattern, and forming a tensile silicon cap on the strained relaxation buffer pattern, the cap being under tensile strain.
摘要翻译：制造半导体器件的方法包括在衬底上形成缓冲图案，缓冲图案包括锗，使缓冲图案重结晶，形成应变弛豫缓冲图案，并在应变张弛缓冲图案上形成拉伸硅帽，在拉伸应变下。

10. 发明授权

US07429504B2 Heterogeneous group IV semiconductor substrates, integrated circuits formed on such substrates, and related methods 有权
标题翻译：异质IV族半导体衬底，形成在这种衬底上的集成电路及相关方法
公开(公告)号：US07429504B2
公开(公告)日：2008-09-30
申请号：US11080737
申请日：2005-03-15
申请人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
发明人： Sung-Min Kim , Kyoung-Hwan Yeo , In-Soo Jung , Si-Young Choi , Dong-Won Kim , Yong-Hoon Son , Young-Eun Lee , Byeong-Chan Lee , Jong-Wook Lee
IPC分类号： H01L21/764 , H01L31/0336
CPC分类号： H01L29/0653 , H01L29/78
摘要： Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
摘要翻译：本发明的实施例包括异质衬底，在这种异质衬底上形成的集成电路，以及形成这种衬底和集成电路的方法。根据本发明的某些实施方案的异质衬底包括第一组IV半导体层（例如，硅），第二组IV图案（例如硅 - 锗图案），其包括第一组IV上的多个单独元件半导体层和第二组IV模式上的第三组IV半导体层（例如，硅外延层）和第一组IV半导体层的多个暴露部分上。在本发明的实施例中可以去除第二组IV图案。在本发明的这些和其它实施例中，第三组IV半导体层可以被平坦化。

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