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1. 发明授权

US06740955B1 Trench device isolation structure 失效
标题翻译：沟槽装置隔离结构
公开(公告)号：US06740955B1
公开(公告)日：2004-05-25
申请号：US10431606
申请日：2003-05-08
申请人： Soo-Jin Hong , Jin-Hwa Heo
发明人： Soo-Jin Hong , Jin-Hwa Heo
IPC分类号： H01L2900
CPC分类号： H01L21/76224
摘要： A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.
摘要翻译：一种形成沟槽器件隔离结构的方法，其中，在半导体衬底的预定区域中形成沟槽之后，依次形成下隔离图案，上衬垫图案和上隔离图案以填充沟槽。在半导体衬底的整个表面上形成下部器件隔离层，然后蚀刻以形成下部隔离图案，使得下部隔离图案的顶表面低于半导体衬底的顶表面。在包括下隔离图案的半导体衬底的整个表面上形成上衬层和上器件隔离层，然后蚀刻以形成上衬垫图案。结果，上衬垫图案覆盖下隔离图案的顶表面并且围绕上隔离图案的底部和侧壁。

2. 发明授权

US06756654B2 Structure of trench isolation and a method of forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US06756654B2
公开(公告)日：2004-06-29
申请号：US10215342
申请日：2002-08-09
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.
摘要翻译：本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层，或在后续过程中门之间的电桥。在第一和第二沟槽中的衬底上形成下隔离层。图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

3. 发明授权

US07160787B2 Structure of trench isolation and a method of forming the same 有权
标题翻译：沟槽隔离结构及其形成方法
公开(公告)号：US07160787B2
公开(公告)日：2007-01-09
申请号：US10791740
申请日：2004-03-04
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： The present invention is directed toward a structure and method by which trench isolation for a wide trench and a narrow trench formed in first and second regions of a substrate may be achieved without formation of a void in an isolation layer, a groove exposing an isolation layer, or an electrical bridge between gates in a subsequent process. A lower isolation layer is formed on the substrate in a first and second trench. The lower isolation layer is patterned to fill a lower region of the first trench, and an upper isolation pattern is formed to fill the second trench and a remainder of the first trench. An aspect ratio of first trench is reduced, thereby preventing the occurrence of a void in the upper isolation layer, or a gap between the upper isolation layer and the substrate.
摘要翻译：本发明涉及一种结构和方法，通过该结构和方法可以实现在衬底的第一和第二区域中形成的宽沟槽和窄沟槽的沟槽隔离，而不会在隔离层中形成空隙，露出隔离层，或在后续过程中门之间的电桥。在第一和第二沟槽中的衬底上形成下隔离层。图案化下部隔离层以填充第一沟槽的下部区域，并且形成上部隔离图案以填充第二沟槽和第一沟槽的其余部分。第一沟槽的纵横比减小，从而防止在上隔离层中发生空隙或上隔离层与基板之间的间隙。

4. 发明授权

US06593207B2 Method of forming a trench device isolation structure with upper liner pattern 失效
标题翻译：形成具有上衬垫图案的沟槽器件隔离结构的方法
公开(公告)号：US06593207B2
公开(公告)日：2003-07-15
申请号：US10121862
申请日：2002-04-15
申请人： Soo-Jin Hong , Jin-Hwa Heo
发明人： Soo-Jin Hong , Jin-Hwa Heo
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a trench device isolation structure, wherein, after forming a trench in a predetermined area of a semiconductor substrate, a lower isolation pattern, an upper liner pattern, and an upper isolation pattern are sequentially formed to fill the trench. A lower device isolation layer is formed on an entire surface of the semiconductor substrate, and then etched to form the lower isolation pattern so that a top surface of the lower isolation pattern is lower than a top surface of the semiconductor substrate. An upper liner layer and an upper device isolation layer are formed on the entire surface of the semiconductor substrate including the lower isolation pattern, and then etched to form the upper liner pattern. As a result, the upper liner pattern covers the top surface of the lower isolation pattern and surrounds the bottom and the sidewall of the upper isolation pattern.
摘要翻译：一种形成沟槽器件隔离结构的方法，其中，在半导体衬底的预定区域中形成沟槽之后，依次形成下隔离图案，上衬垫图案和上隔离图案以填充沟槽。在半导体衬底的整个表面上形成下部器件隔离层，然后蚀刻以形成下部隔离图案，使得下部隔离图案的顶表面低于半导体衬底的顶表面。在包括下隔离图案的半导体衬底的整个表面上形成上衬层和上器件隔离层，然后蚀刻以形成上衬垫图案。结果，上衬垫图案覆盖下隔离图案的顶表面并且围绕上隔离图案的底部和侧壁。

5. 发明授权

US06566229B2 Method of forming an insulating layer in a trench isolation type semiconductor device 失效
公开(公告)号：US06566229B2
公开(公告)日：2003-05-20
申请号：US09991928
申请日：2001-11-26
申请人： Soo-Jin Hong , Moon-Han Park , Ju-Seon Goo , Jin-Hwa Heo , Hong-Gun Kim , Eun-Kee Hong
发明人： Soo-Jin Hong , Moon-Han Park , Ju-Seon Goo , Jin-Hwa Heo , Hong-Gun Kim , Eun-Kee Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH2NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

6. 发明授权

US07351661B2 Semiconductor device having trench isolation layer and a method of forming the same 失效
标题翻译：具有沟槽隔离层的半导体器件及其形成方法
公开(公告)号：US07351661B2
公开(公告)日：2008-04-01
申请号：US10734354
申请日：2003-12-12
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L21/302
CPC分类号： H01L21/76224 , Y10S438/978
摘要： A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.
摘要翻译：提供了一种在半导体衬底中具有沟槽隔离层的半导体器件，其中沟槽隔离层包括氮化硅衬垫，氧化硅衬垫; 以及掩埋层，其中所述掩埋层包括用于填充所述沟槽隔离层的下部的第一掩埋层和用于填充所述沟槽隔离层的上部的第二掩埋层。半导体器件优选地还包括设置在半导体衬底和氮化硅衬垫之间的氧化硅层。氧化硅层包括在超过约800℃的温度下致密化的热氧化物层。

7. 发明授权

US06683354B2 Semiconductor device having trench isolation layer and a method of forming the same 失效
标题翻译：具有沟槽隔离层的半导体器件及其形成方法
公开(公告)号：US06683354B2
公开(公告)日：2004-01-27
申请号：US09990740
申请日：2001-11-16
申请人： Jin-Hwa Heo , Soo-Jin Hong
发明人： Jin-Hwa Heo , Soo-Jin Hong
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , Y10S438/978
摘要： A semiconductor device having a trench isolation layer in a semiconductor substrate is provided, wherein the trench isolation layer includes a silicon nitride liner, a silicon oxide liner; and a buried layer, wherein the buried layer includes a first buried layer for filling a lower part of the trench isolation layer and a second buried layer for filling an upper part of the trench isolation layer. A semiconductor device preferably further includes a silicon oxide layer disposed between the semiconductor substrate and the silicon nitride liner. The silicon oxide layer includes a thermal oxide layer densified at a temperature over about 800° C.
摘要翻译：提供了一种在半导体衬底中具有沟槽隔离层的半导体器件，其中沟槽隔离层包括氮化硅衬垫，氧化硅衬垫; 以及掩埋层，其中所述掩埋层包括用于填充所述沟槽隔离层的下部的第一掩埋层和用于填充所述沟槽隔离层的上部的第二掩埋层。半导体器件优选地还包括设置在半导体衬底和氮化硅衬垫之间的氧化硅层。氧化硅层包括在超过约800℃的温度下致密化的热氧化物层。

8. 发明授权

US07514744B2 Semiconductor device including carrier accumulation layers 失效
标题翻译：半导体器件包括载流子堆积层
公开(公告)号：US07514744B2
公开(公告)日：2009-04-07
申请号：US11322335
申请日：2005-12-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Soo-Jin Hong , Guk-Hyon Yon
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/4983 , H01L21/28247 , H01L21/28273 , H01L21/28282 , H01L29/6659 , H01L29/7833 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes a gate structure on a channel region of a semiconductor substrate adjacent to a source/drain region therein and a surface insulation layer directly on the source/drain region of the substrate adjacent to the gate structure. The device further includes a spacer on a sidewall of the gate structure adjacent to the source/drain region. A portion of the surface insulation layer adjacent the gate structure is sandwiched between the substrate and the spacer. An interface between the surface insulation layer and the source/drain region includes a plurality of interfacial states. Portions of the source/drain region immediately adjacent the interface define a carrier accumulation layer having a greater carrier concentration than other portions thereof. The carrier accumulation layer extends along the interface under the spacer. Related methods are also discussed.
摘要翻译：半导体器件包括与半导体衬底的与源极/漏极区域相邻的沟道区域上的栅极结构，以及直接位于与栅极结构相邻的衬底的源极/漏极区域上的表面绝缘层。该器件还包括邻近源极/漏极区的栅极结构的侧壁上的间隔物。与栅极结构相邻的表面绝缘层的一部分夹在基板和间隔件之间。表面绝缘层与源极/漏极区之间的界面包括多个界面状态。紧邻界面的源极/漏极区域的部分限定了具有比其它部分更大的载流子浓度的载流子积累层。载体积聚层沿着间隔物下的界面延伸。还讨论了相关方法。

9. 发明授权

US06251746B1 Methods of forming trench isolation regions having stress-reducing nitride layers therein 失效
标题翻译：在其中形成具有应力减小氮化物层的沟槽隔离区的方法
公开(公告)号：US06251746B1
公开(公告)日：2001-06-26
申请号：US09415475
申请日：1999-10-08
申请人： Soo-Jin Hong , Yung-Seob Yu , Bon-Young Koo , Byung-Ki Kim , Seung-Mok Shin
发明人： Soo-Jin Hong , Yung-Seob Yu , Bon-Young Koo , Byung-Ki Kim , Seung-Mok Shin
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： Methods of forming trench isolation regions include the steps of forming a trench masking layer comprising a first material (e.g., polysilicon) on a semiconductor substrate and then etching a trench in the semiconductor substrate, using the trench masking layer as etching mask. A trench nitride layer comprising a second material different from the first material is then formed on a sidewall of the trench and on a sidewall of the trench masking layer. The trench is then filled with a trench insulating material (e.g., USG). The trench masking layer is then removed by selectively etching the trench masking layer with an etchant that selectively etches the first material at a higher rate than the second material. This step of removing the trench masking layer results in exposure of a protruding portion of the trench nitride layer but does not cause the trench nitride layer to become recessed. The trench insulating material and the trench nitride layer are then etched back to define the trench isolation region.
摘要翻译：形成沟槽隔离区的方法包括以下步骤：使用沟槽掩模层作为蚀刻掩模，在半导体衬底上形成包含第一材料（例如多晶硅）的沟槽屏蔽层，然后蚀刻半导体衬底中的沟槽。然后在沟槽的侧壁和沟槽掩模层的侧壁上形成包括不同于第一材料的第二材料的沟槽氮化物层。然后用沟槽绝缘材料（例如USG）填充沟槽。然后通过用比第二材料更高的速率选择性地蚀刻第一材料的蚀刻剂选择性蚀刻沟槽掩模层来去除沟槽掩模层。去除沟槽屏蔽层的这个步骤导致了沟槽氮化物层的突出部分的曝光，但是不会使沟槽氮化物层变凹陷。然后将沟槽绝缘材料和沟槽氮化物层回蚀刻以限定沟槽隔离区域。

10. 发明授权

US06699799B2 Method of forming a semiconductor device 有权
标题翻译：形成半导体器件的方法
公开(公告)号：US06699799B2
公开(公告)日：2004-03-02
申请号：US10134747
申请日：2002-04-30
申请人： Dong-Ho Ahn , Soo-Jin Hong , Jung-Il Lee , Kyung-won Park
发明人： Dong-Ho Ahn , Soo-Jin Hong , Jung-Il Lee , Kyung-won Park
IPC分类号： H01L21469
CPC分类号： H01L21/0234 , H01L21/02134 , H01L21/02164 , H01L21/02282 , H01L21/02348 , H01L21/31053 , H01L21/316 , H01L21/76229
摘要： A method of forming a semiconductor device includes a liner is conformally stacked on a semiconductor substrate before coating an SOG layer thereon, and then curing the SOG layer, preferably in an ambient of oxygen radicals formed at a temperature of 1000° C. or higher when oxygen and hydrogen are supplied. The oxygen radicals are preferably formed by irradiating ultraviolet rays to ozone or forming oxygen plasma. The SOG layer is preferably made of a polysilazane-based material that may promote a conversion of the SOG layer into a silicon oxide layer.
摘要翻译：一种形成半导体器件的方法包括：在涂覆SOG层之前，在半导体衬底上保形地层叠衬垫，然后固化SOG层，优选在1000℃或更高温度下形成的氧自由基的环境中固化供应氧气和氢气。氧自由基优选通过将紫外线照射到臭氧或形成氧等离子体来形成。 SOG层优选由可以促进SOG层转化为氧化硅层的基于聚硅氮烷的材料制成。

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