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1. 发明授权

US06518833B2 Low voltage PVT insensitive MOSFET based voltage reference circuit 失效
标题翻译：低压PVT不敏感MOSFET基电压基准电路
公开(公告)号：US06518833B2
公开(公告)日：2003-02-11
申请号：US09470275
申请日：1999-12-22
申请人： Siva G. Narendra , Krishnamurthy Soumyanath , Vivek K. De
发明人： Siva G. Narendra , Krishnamurthy Soumyanath , Vivek K. De
IPC分类号： G05F110
CPC分类号： G05F3/242 , G05F3/262
摘要： Methods and apparatus for generating a MOSFET based voltage reference circuit with automatic trimming of resistors to compensate for process and supply voltage variations and to improve the accuracy of a MOSFET based reference voltage circuit, a temperature compensated MOSFET based reference voltage, and arbitrary translation of the MOSFET based reference voltage with or without trimming are provided.
摘要翻译：用于产生基于MOSFET的电压参考电路的方法和装置，其具有自动微调电阻器以补偿过程和电源电压变化并提高基于MOSFET的参考电压电路的精度，基于温度补偿的MOSFET的参考电压和任意的提供了具有或不具有微调功能的基于MOSFET的参考电压。

2. 发明授权

US06177788B1 Nonlinear body effect compensated MOSFET voltage reference 有权
标题翻译：非线性体效应补偿MOSFET参考电压
公开(公告)号：US06177788B1
公开(公告)日：2001-01-23
申请号：US09470291
申请日：1999-12-22
申请人： Siva G. Narendra , Krishnamurthy Soumyanath , Vivek K. De
发明人： Siva G. Narendra , Krishnamurthy Soumyanath , Vivek K. De
IPC分类号： G05F316
CPC分类号： G05F3/262 , Y10S323/907
摘要： A nonlinear body effect compensation circuit includes a number of PMOSFETs, each having an identical current flow, with two of the PMOSFETs having different sizes, and two of the PMOSFETs having different body to source voltages. The different body to source voltages of the two PMOSFETs affect the gate to source voltage of the PMOSFETs in a manner that allows compensation of nonlinear body effects as a function of temperature. A voltage proportional to absolute temperature (VPTAT) is generated as a difference between the gate to source voltages of the two PMOSFETs having different sizes, and a voltage not proportional to absolute temperature (VnPTAT) is generated as a difference between the gate to source voltages of the two PMOSFETs having different body to source voltages.
摘要翻译：非线性体效应补偿电路包括多个具有相同电流的PMOSFET，其中两个PMOSFET具有不同的尺寸，并且两个PMOSFET具有不同的体电源电压。两个PMOSFET的不同体电源电压以允许补偿作为温度的函数的非线性体效应的方式影响PMOSFET的栅极至源极电压。产生与绝对温度成比例的电压（VPTAT）作为具有不同尺寸的两个PMOSFET的栅极 - 源极电压之间的差异，并且产生与绝对温度（VnPTAT）成比例的电压作为栅极 - 源极电压之间的差的两个PMOSFET具有不同的体电源电压。

3. 发明申请

US20100219516A1 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

4. 发明申请

US20100145895A1 COMPONENT RELIABILITY BUDGETING SYSTEM 有权
标题翻译：组件可靠性预算系统
公开(公告)号：US20100145895A1
公开(公告)日：2010-06-10
申请号：US12704789
申请日：2010-02-12
申请人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
发明人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
IPC分类号： G06F15/18 , G06F1/28 , G06F1/32 , G06N5/02
CPC分类号： G06F1/206 , Y02D10/16
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译：系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及温度信息。一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

5. 发明授权

US07376849B2 Method, apparatus and system of adjusting one or more performance-related parameters of a processor 有权
标题翻译：调整处理器的一个或多个性能相关参数的方法，装置和系统
公开(公告)号：US07376849B2
公开(公告)日：2008-05-20
申请号：US10879486
申请日：2004-06-30
申请人： James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要翻译：本发明的实施例提供了一种用于基于与处理器核心的操作条件相关的至少一个操作参数来动态地调整处理器核心的一个或多个与性能有关的参数的方法，装置和系统。

6. 发明授权

US07236045B2 Bias generator for body bias 有权
标题翻译：偏置发生器用于身体偏倚
公开(公告)号：US07236045B2
公开(公告)日：2007-06-26
申请号：US11038394
申请日：2005-01-21
申请人： James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.
摘要翻译：提供偏置发生器，其包括中心偏置发生器以提供第一偏置电压和局部偏置发生器以接收第一偏置电压并提供第二偏置电压。中心偏置发生器可以包括基本上对应于局部偏置发生器的复制偏压发生器电路。

7. 发明授权

US06975005B2 Current reference apparatus and systems 失效
标题翻译：当前的参考设备和系统
公开(公告)号：US06975005B2
公开(公告)日：2005-12-13
申请号：US10689128
申请日：2003-10-20
申请人： Siva G. Narendra , Stephen H. Tang , Zachary Keer , Vivek K. De
发明人： Siva G. Narendra , Stephen H. Tang , Zachary Keer , Vivek K. De
IPC分类号： G05F3/24 , H01L29/76
CPC分类号： G05F3/245 , Y10S257/919
摘要： A current reference, which may be fabricated independently, on a die, as part of an integrated circuit, or a system, or in various other forms, is disclosed. The current reference may include a voltage source having a substantially temperature stable output voltage, a first semiconductor device biased by the substantially temperature stable output voltage to provide a first output current, and a second semiconductor device providing a second output current, wherein a reference current is provided approximately equal to the difference between the first and second output currents.
摘要翻译：公开了可以在芯片上作为集成电路或系统的一部分或以各种其它形式单独制造的电流基准。电流参考可以包括具有基本上温度稳定的输出电压的电压源，由基本上温度稳定的输出电压偏置以提供第一输出电流的第一半导体器件，以及提供第二输出电流的第二半导体器件，其中参考电流被提供大致等于第一和第二输出电流之间的差。

8. 发明授权

US06744301B1 System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise 有权
标题翻译：系统使用身体偏置的睡眠晶体管来减少泄漏功率，同时最大限度地降低性能损失和噪音
公开(公告)号：US06744301B1
公开(公告)日：2004-06-01
申请号：US09707528
申请日：2000-11-07
申请人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G05F302
CPC分类号： G05F3/205
摘要： A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
摘要翻译：公开了一种降低泄漏功率同时最小化性能损失和噪声的系统和方法。根据本发明的一个实施例，该系统包括至少一个休眠晶体管，其可操作地耦合在系统电源和由系统电源供电的至少一个电路之间，以控制对电路的功率的施加。休眠晶体管也可操作地耦合以接收睡眠控制信号以打开和关闭睡眠晶体管。身体偏置电压发生器可操作地耦合到至少一个睡眠晶体管的主体，以在休眠晶体管不可操作或空闲时基本上减少泄漏电流，并且当晶体管通过降低工作时改善睡眠晶体管的操作特性休眠晶体管的性能损失，并减少噪声对电路和其他器件的影响。

9. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

10. 发明授权

US06411156B1 Employing transistor body bias in controlling chip parameters 有权
标题翻译：采用晶体管体偏置来控制芯片参数
公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译：在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号控制电路。在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

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