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1. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

2. 发明授权

US06593799B2 Circuit including forward body bias from supply voltage and ground nodes 有权
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06593799B2
公开(公告)日：2003-07-15
申请号：US09957996
申请日：2001-09-21
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H03K301
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

3. 发明授权

US06411156B1 Employing transistor body bias in controlling chip parameters 有权
标题翻译：采用晶体管体偏置来控制芯片参数
公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
申请人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
发明人： Shekhar Y. Borkar , Vivek K. De , Ali Keshavarzi , Siva G. Narendra
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译：在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号控制电路。在一些实施例中，本发明涉及包括集成电路的系统。该系统包括晶体管的电路。该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。

4. 发明授权

US06300819B1 Circuit including forward body bias from supply voltage and ground nodes 失效
标题翻译：电路包括电源电压和接地节点的正向偏置
公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译：本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

5. 发明授权

US06100751A Forward body biased field effect transistor providing decoupling capacitance 失效
标题翻译：正向偏置场效应晶体管提供去耦电容
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译：在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于第一组场效应晶体管的阈值电压。在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。

6. 发明授权

US06734498B2 Insulated channel field effect transistor with an electric field terminal region 有权
公开(公告)号：US06734498B2
公开(公告)日：2004-05-11
申请号：US09165483
申请日：1998-10-02
申请人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
发明人： Ali Keshavarzi , Vivek K. De , Siva G. Narendra
IPC分类号： H01L2701
CPC分类号： H01L29/78603 , H01L21/84 , H01L27/1203 , H01L29/78606 , H01L29/78645 , H01L29/78648
摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

7. 发明授权

US06632686B1 Silicon on insulator device design having improved floating body effect 失效
标题翻译：硅绝缘体器件设计具有改善的浮体效应
公开(公告)号：US06632686B1
公开(公告)日：2003-10-14
申请号：US09672696
申请日：2000-09-29
申请人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
发明人： Ali Keshavarzi , Siva G. Narendra , James W. Tschanz , Vivek K. De
IPC分类号： H01L2166
CPC分类号： G06F17/5068 , G06F17/5063 , H01L27/1203
摘要： A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.
摘要翻译：提供了一种用于设计电子设备的方法。这可以包括确定电子设备的设计的电容比并改变设计以增加所述电子设备的电容比。电容比可以是C dj /（C dj + C sj + C BOX ），其中C dj 是漏 - 体结的电容C sj 是源体结的电容，C BOX 是掩埋氧化物层的电容。

8. 发明授权

US06218895B1 Multiple well transistor circuits having forward body bias 失效
标题翻译：具有前向偏置的多个阱晶体管电路
公开(公告)号：US06218895B1
公开(公告)日：2001-04-17
申请号：US09078424
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.
摘要翻译：在本发明的一个实施例中，半导体电路包括衬底和形成在衬底中的第一阱。在第一阱中形成第一组场效应晶体管，并且具有第一主体。该电路包括第一体电压，以使第一组场效应晶体管偏转第一体。电路包括第一隔离结构，以在第一阱中容纳第一体电压。在另一实施例中，电路还包括具有非正向主体偏置的第二组场效应晶体管，并且第一隔离结构防止第一体电压影响第二组场效应晶体管的主体的电压。在另一个实施例中，与第二阱相邻的第二隔离结构在保持第二组场效应晶体管的第二阱中包含第二体电压。

9. 发明授权

US06825687B2 Selective cooling of an integrated circuit for minimizing power loss 有权
标题翻译：集成电路的选择性冷却，以最大限度地减少功率损耗
公开(公告)号：US06825687B2
公开(公告)日：2004-11-30
申请号：US10230466
申请日：2002-08-29
申请人： Ali Keshavarzi , Jaume A. Segura , Siva G. Narendra , Vivek K. De
发明人： Ali Keshavarzi , Jaume A. Segura , Siva G. Narendra , Vivek K. De
IPC分类号： H03K1716
CPC分类号： H03K19/0016 , H01L27/0251
摘要： An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.
摘要翻译：一种用于降低在集成电路中使用的晶体管的泄漏电流的装置和方法，其选择性地将集成电路中的处理器电路切换到待机状态。包括冷却装置并且选择性地位于集成电路的紧邻用于在主动状态和待机状态之间切换处理器电路的晶体管的区域中。冷却装置冷却晶体管，以改善其泄漏和有功电流状态，从而提高晶体管的效率并减少其漏电流。

10. 发明授权

US06232827B1 Transistors providing desired threshold voltage and reduced short channel effects with forward body bias 失效
标题翻译：晶体管提供期望的阈值电压和减少的短通道效应与前向偏置
公开(公告)号：US06232827B1
公开(公告)日：2001-05-15
申请号：US09078388
申请日：1998-05-13
申请人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
发明人： Vivek K. De , Ali Keshavarzi , Siva G. Narendra , Shekhar Y. Borkar
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.
摘要翻译：在一个实施例中，半导体电路包括具有主体的第一组场效应晶体管和包括净通道掺杂水平DL1的参数。该电路还包括导体，用于向主体提供第一电压以使第一组晶体管偏置，第一组晶体管在正向偏置时具有正向偏置阈值电压（VtFBB），其中DL1至少为25 高于第一组晶体管中的净通道掺杂水平，其将导致零体偏置阈值电压等于VtFBB，其中除了净通道掺杂水平之外的参数不变。在另一实施例中，半导体电路包括第一电路，其包括具有主体的第一组场效应晶体管。电路还包括第一电压源，以向主体提供第一电压，使得场效应晶体管具有正向体偏置，第一电压处于导致电路经历软错误故障率降低的水平，与当电路没有正向偏置时。

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