专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100219516A1 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

2. 发明授权

US08288846B2 Power management integrated circuit 有权
标题翻译：电源管理集成电路
公开(公告)号：US08288846B2
公开(公告)日：2012-10-16
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495 , H01L23/52 , H01L21/00
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

3. 发明申请

US20140089687A1 POWER MANAGEMENT INTEGRATED CIRCUIT 审中-公开
标题翻译：电源管理集成电路
公开(公告)号：US20140089687A1
公开(公告)日：2014-03-27
申请号：US13626357
申请日：2012-09-25
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , H01L23/34 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , Y02D10/126 , Y02D10/172
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译：公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。

4. 发明授权

US07051295B2 IC design process including automated removal of body contacts from MOSFET devices 有权
标题翻译： IC设计过程包括从MOSFET器件自动移除主体触点
公开(公告)号：US07051295B2
公开(公告)日：2006-05-23
申请号：US10746759
申请日：2003-12-23
申请人： Siva G. Narendra , Daniel S. Klowden , James W. Tschanz , Nitin Borkar , Vivek K. De
发明人： Siva G. Narendra , Daniel S. Klowden , James W. Tschanz , Nitin Borkar , Vivek K. De
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： An apparatus for and method of modifying an IC design layout of an integrated circuit, comprising: accessing an initial IC design layout, with the initial layout including a plurality of MOSFET devices having a common substrate; and removing a plurality of body contacts of the MOSFET devices to create a first modified IC design layout.
摘要翻译：一种用于修改集成电路的IC设计布局的装置和方法，包括：访问初始IC设计布局，初始布局包括具有公共衬底的多个MOSFET器件; 以及去除所述MOSFET器件的多个体接触以产生第一修改的IC设计布局。

5. 发明申请

US20100145895A1 COMPONENT RELIABILITY BUDGETING SYSTEM 有权
标题翻译：组件可靠性预算系统
公开(公告)号：US20100145895A1
公开(公告)日：2010-06-10
申请号：US12704789
申请日：2010-02-12
申请人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
发明人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
IPC分类号： G06F15/18 , G06F1/28 , G06F1/32 , G06N5/02
CPC分类号： G06F1/206 , Y02D10/16
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译：系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及温度信息。一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

6. 发明授权

US07376849B2 Method, apparatus and system of adjusting one or more performance-related parameters of a processor 有权
标题翻译：调整处理器的一个或多个性能相关参数的方法，装置和系统
公开(公告)号：US07376849B2
公开(公告)日：2008-05-20
申请号：US10879486
申请日：2004-06-30
申请人： James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Stephen H. Tang , Siva G. Narendra , Vivek K. De
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要翻译：本发明的实施例提供了一种用于基于与处理器核心的操作条件相关的至少一个操作参数来动态地调整处理器核心的一个或多个与性能有关的参数的方法，装置和系统。

7. 发明授权

US07236045B2 Bias generator for body bias 有权
标题翻译：偏置发生器用于身体偏倚
公开(公告)号：US07236045B2
公开(公告)日：2007-06-26
申请号：US11038394
申请日：2005-01-21
申请人： James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Stephen H. Tang , Victor Zia , Badarinath Kommandur , Siva G. Narendra , Vivek K. De
IPC分类号： G05F1/10
CPC分类号： G05F3/205
摘要： A bias generator is provided that includes a central bias generator to provide a first bias voltage and a local bias generator to receive the first bias voltage and to provide a second bias voltage. The central bias generator may include a replica bias generator circuit substantially corresponding to the local bias generator.
摘要翻译：提供偏置发生器，其包括中心偏置发生器以提供第一偏置电压和局部偏置发生器以接收第一偏置电压并提供第二偏置电压。中心偏置发生器可以包括基本上对应于局部偏置发生器的复制偏压发生器电路。

8. 发明授权

US06744301B1 System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise 有权
标题翻译：系统使用身体偏置的睡眠晶体管来减少泄漏功率，同时最大限度地降低性能损失和噪音
公开(公告)号：US06744301B1
公开(公告)日：2004-06-01
申请号：US09707528
申请日：2000-11-07
申请人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G05F302
CPC分类号： G05F3/205
摘要： A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
摘要翻译：公开了一种降低泄漏功率同时最小化性能损失和噪声的系统和方法。根据本发明的一个实施例，该系统包括至少一个休眠晶体管，其可操作地耦合在系统电源和由系统电源供电的至少一个电路之间，以控制对电路的功率的施加。休眠晶体管也可操作地耦合以接收睡眠控制信号以打开和关闭睡眠晶体管。身体偏置电压发生器可操作地耦合到至少一个睡眠晶体管的主体，以在休眠晶体管不可操作或空闲时基本上减少泄漏电流，并且当晶体管通过降低工作时改善睡眠晶体管的操作特性休眠晶体管的性能损失，并减少噪声对电路和其他器件的影响。

9. 发明授权

US07444528B2 Component reliability budgeting system 有权
标题翻译：组件可靠性预算系统
公开(公告)号：US07444528B2
公开(公告)日：2008-10-28
申请号：US11295400
申请日：2005-12-06
申请人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
发明人： Siva G. Narendra , James W. Tschanz , Vivek K. De , Stephen H. Tang
IPC分类号： G06F1/26 , G06F1/00
CPC分类号： G06F1/206 , Y02D10/16
摘要： A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.
摘要翻译：系统可以包括获取表示提供给电气部件的过去电源电压的电源电压信息，基于电源电压信息获取表示电气部件的过去温度的温度信息和电气部件的性能特性的控制，以及温度信息。一些实施例还可以包括基于电源电压信息，温度信息以及电气部件的可靠性规格以及基于可靠性裕度的性能特性的改变来确定可靠性裕度。

10. 发明授权

US06917237B1 Temperature dependent regulation of threshold voltage 失效
标题翻译：温度依赖调节阈值电压
公开(公告)号：US06917237B1
公开(公告)日：2005-07-12
申请号：US10792262
申请日：2004-03-02
申请人： James W. Tschanz , Mircea R. Stan , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Mircea R. Stan , Siva G. Narendra , Vivek K. De
IPC分类号： G05F3/20 , G05F3/26 , H03K3/01
CPC分类号： G05F3/262 , G05F3/205
摘要： Embodiments circuits provide a transistor body bias voltage so that the ratio of ION to IOFF is constant over a range of temperature, where ION is a transistor current when ON and IOFF is a (leakage) transistor current when OFF. In one embodiment, a nFET is biased to provide ION to a current mirror that sources a current AION to a node, a nFET is biased to provide IOFF to a current mirror that sinks a current BIOFF from the node, and an amplifier provides feedback from the node to the body terminals of the nFETs so that at steady state AION=BIOFF, where A and B are constants independent over a range of temperature. In this way, the ratio ION/IOFF is maintained at B/A for some range of temperatures. Other embodiments are described and claimed.
摘要翻译：实施例电路提供晶体管体偏置电压，使得I ON / OFF与I OFF之间的比率在温度范围内是恒定的，其中I < 是ON时的晶体管电流，当OFF时，I 是晶体管电流（泄漏）。在一个实施例中，nFET被偏置以将电流镜提供给电流反射镜，该电流镜将节点的当前AI导通，nFET被偏置以提供I < OFF 到从节点吸收当前BI OFF的电流镜，并且放大器从节点向nFET的体式终端提供反馈，使得在稳态AI < ON = BI ，其中A和B在温度范围内是常数独立的。以这种方式，在一些温度范围内，比率I ON / OFF / OFF保持在B / A。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式