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1. 发明授权

US06744301B1 System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise 有权
标题翻译：系统使用身体偏置的睡眠晶体管来减少泄漏功率，同时最大限度地降低性能损失和噪音
公开(公告)号：US06744301B1
公开(公告)日：2004-06-01
申请号：US09707528
申请日：2000-11-07
申请人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： James W. Tschanz , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G05F302
CPC分类号： G05F3/205
摘要： A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.
摘要翻译：公开了一种降低泄漏功率同时最小化性能损失和噪声的系统和方法。根据本发明的一个实施例，该系统包括至少一个休眠晶体管，其可操作地耦合在系统电源和由系统电源供电的至少一个电路之间，以控制对电路的功率的施加。休眠晶体管也可操作地耦合以接收睡眠控制信号以打开和关闭睡眠晶体管。身体偏置电压发生器可操作地耦合到至少一个睡眠晶体管的主体，以在休眠晶体管不可操作或空闲时基本上减少泄漏电流，并且当晶体管通过降低工作时改善睡眠晶体管的操作特性休眠晶体管的性能损失，并减少噪声对电路和其他器件的影响。

2. 发明授权

US06496040B1 Trading off gate delay versus leakage current using device stack effect 失效
标题翻译：使用器件堆栈效应来计算门延迟与泄漏电流
公开(公告)号：US06496040B1
公开(公告)日：2002-12-17
申请号：US09823633
申请日：2001-03-30
申请人： Siva G. Narendra , Yibin Ye , Vivek K. De
发明人： Siva G. Narendra , Yibin Ye , Vivek K. De
IPC分类号： H01L2500
CPC分类号： G06F17/5068
摘要： A stack device is provided to obtain a stack effect. The stack device includes at least first and second active components. The first and second active components have first and second device widths, respectively. The first and second device widths are then selected to provide a desired leakage current and gate delay time for the stack device. The selection includes adjusting the first and second device widths while keeping a sum of the device widths constant.
摘要翻译：提供堆栈设备以获得堆栈效应。堆叠装置至少包括第一和第二活动部件。第一和第二有源部件分别具有第一和第二器件宽度。然后选择第一和第二器件宽度以为堆叠器件提供期望的漏电流和栅极延迟时间。该选择包括在保持设备宽度的总和恒定的同时调整第一和第二设备宽度。

3. 发明授权

US06653866B2 Domino logic with output predischarge 有权
公开(公告)号：US06653866B2
公开(公告)日：2003-11-25
申请号：US10277009
申请日：2002-10-21
申请人： Siva G. Narendra , Yibin Ye , Vivek K. De
发明人： Siva G. Narendra , Yibin Ye , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/01728
摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

4. 发明授权

US06275071B1 Domino logic circuit and method 有权
标题翻译：多米诺逻辑电路和方法
公开(公告)号：US06275071B1
公开(公告)日：2001-08-14
申请号：US09474533
申请日：1999-12-29
申请人： Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit includes input connections to receive a clock signal and at least one input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising precharge circuitry, and a static stage that comprises discharge circuitry. In another embodiment, the domino logic circuit includes a dynamic stage comprising discharge circuitry, and a static stage that comprises precharge circuitry. Different configurations and transistor types have also been described. The circuitry can provide improved speed performance, or increase noise immunity.
摘要翻译：多米诺逻辑电路包括用于接收时钟信号和至少一个输入数据信号的输入连接。在一个实施例中，多米诺逻辑电路包括包括预充电电路的动态级和包括放电电路的静态级。在另一个实施例中，多米诺骨牌逻辑电路包括包括放电电路的动态级和包括预充电电路的静态级。还描述了不同的配置和晶体管类型。该电路可以提供改进的速度性能，或提高抗噪声能力。

5. 发明授权

US06519176B1 Dual threshold SRAM cell for single-ended sensing 失效
标题翻译：用于单端感测的双阈值SRAM单元
公开(公告)号：US06519176B1
公开(公告)日：2003-02-11
申请号：US09675579
申请日：2000-09-29
申请人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Fatih Hamzaoglu , Ali Keshavarzi , Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： G11C1100
CPC分类号： G11C11/412
摘要： A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.
摘要翻译：描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。一个通道晶体管具有比另一个晶体管更低的阈值电压。较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。

6. 发明授权

US06492837B1 Domino logic with output predischarge 失效
标题翻译：具有输出预放电功能的Domino逻辑
公开(公告)号：US06492837B1
公开(公告)日：2002-12-10
申请号：US09527344
申请日：2000-03-17
申请人： Siva G. Narendra , Yibin Ye , Vivek K. De
发明人： Siva G. Narendra , Yibin Ye , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963 , H03K19/01728
摘要： A domino logic circuit is provided. The circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage which serves as an output receiver circuit, the output of which is the output of the domino logic circuit. An n-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.
摘要翻译：提供多米诺骨牌逻辑电路。电路包括耦合在动态输出节点和高电压连接之间的n沟道时钟晶体管，时钟晶体管的栅极进一步耦合以接收反相时钟信号。第一反相器具有连接到动态输出节点的输入。具有连接到动态输出节点的输入的第二反相器包括静态CMOS电路级，其作为输出接收器电路，其输出是多米诺逻辑电路的输出。 N沟道电平保持器晶体管连接在动态输出节点和高压连接之间，电平保持晶体管的栅极连接到第一个反相器的输出端。下拉电路连接在动态输出节点和低压连接之间。输出预放电晶体管连接在静态CMOS电路的输出端和低电压连接端之间，并在其门口耦合并由时钟信号控制。

7. 发明授权

US06486706B2 Domino logic with low-threshold NMOS pull-up 失效
公开(公告)号：US06486706B2
公开(公告)日：2002-11-26
申请号：US09731515
申请日：2000-12-06
申请人： Yibin Ye , Siva G. Narendra , Vivek K. De
发明人： Yibin Ye , Siva G. Narendra , Vivek K. De
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit includes an n-channel clock transistor coupled between a dynamic output node and a high voltage connection, the gate of the clock transistor further coupled to receive an inverse clock signal. A first inverter has an input connected to the dynamic output node. A second inverter with an input connected to the dynamic output node comprises a static CMOS circuit stage, the output of which is the output of the domino logic circuit. A p-channel level keeper transistor is connected between the dynamic output node and the high voltage connection, and the gate of the level keeper transistor is connected to the output of the first inverter. A pull-down circuit is connected between the dynamic output node and a low-voltage connection. A pull-up circuit is connected between the static CMOS circuit output and the high voltage connection. An output predischarge transistor is connected between the output of the static CMOS circuit and the low voltage connection, and is coupled to and controlled by a clock signal at its gate.

8. 发明授权

US07684520B2 Method and apparatus for bus repeater tapering 有权
标题翻译：总线中继器渐变的方法和装置
公开(公告)号：US07684520B2
公开(公告)日：2010-03-23
申请号：US10334746
申请日：2002-12-31
申请人： James W. Tschanz , Muhammad M. Khellah , Yibin Ye , Vivek K. De
发明人： James W. Tschanz , Muhammad M. Khellah , Yibin Ye , Vivek K. De
IPC分类号： H04L27/00
CPC分类号： H04L25/242
摘要： A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.
摘要翻译：一种用于总线中继器锥形化的方法和装置。选择一个传输线路的一部分上的中继器的大小以传播特定速率的信号转换。选择在另一传输线的基本平行部分上的中继器的尺寸以便以不同的速率传播第二信号转换。因此，可以减小两条传输线之间的最坏情况电容耦合系数。

9. 发明授权

US07423899B2 SRAM device having forward body bias control 有权
标题翻译：具有前向偏置控制的SRAM器件
公开(公告)号：US07423899B2
公开(公告)日：2008-09-09
申请号：US10812894
申请日：2004-03-31
申请人： Stephen H. Tang , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz
发明人： Stephen H. Tang , Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De , James W. Tschanz
IPC分类号： G11C11/00 , G11C5/14
CPC分类号： G11C11/412
摘要： A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.
摘要翻译：提供具有多个存储单元的SRAM器件。每个存储单元可以包括以交叉耦合的反相器配置耦合的多个晶体管。 NMOS晶体管可以以交叉耦合的反相器配置耦合到两个PMOS晶体管的主体，以便向交叉耦合的反相器配置的PMOS晶体管施加正向偏置。功率控制单元可以控制每个PMOS晶体管的电源电压，并且基于存储器单元的STANDBY模式将开关信号施加到NMOS晶体管。

10. 发明授权

US07342845B2 Method and apparatus to clamp SRAM supply voltage 有权
标题翻译： SRAM电源电压的方法和装置
公开(公告)号：US07342845B2
公开(公告)日：2008-03-11
申请号：US11320789
申请日：2005-12-30
申请人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
发明人： Dinesh Somasekhar , Muhammad M. Khellah , Yibin Ye , Vivek K. De , James W. Tschanz , Stephen H. Tang
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C5/147 , G11C11/413
摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.
摘要翻译：提供了一种用于限制SRAM装置中的电源电压下降以保持IDLE状态期间存储器的状态的装置和方法。该装置可以包括存储器阵列，睡眠装置和钳位电路。钳位电路可以被配置为当存储器阵列上的电压降低于预设电压并且存储器阵列处于空闲状态时激活睡眠装置。

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