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1. 发明授权

US07330052B2 Area efficient fractureable logic elements 有权
$Area efficient fractureable logic elements$
标题翻译：区域有效的可断裂逻辑元件
公开(公告)号：US07330052B2
公开(公告)日：2008-02-12
申请号：US11234538
申请日：2005-09-22
申请人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
发明人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1737
摘要： A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.
摘要翻译：可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。每个2-LUT包括四个存储元件。每个存储器元件被配置为保持一个数据位。可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集一组六个输入。

2. 发明授权

US07368942B1 Dedicated resource interconnects 有权
标题翻译：专用资源互连
公开(公告)号：US07368942B1
公开(公告)日：2008-05-06
申请号：US11351882
申请日：2006-02-09
申请人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
发明人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.
摘要翻译：本发明一般来说涉及利用与可编程逻辑器件中的数字信号处理块相邻的逻辑组的现有输出来扩展数字信号处理块的功能。来自逻辑组的输出被用作为数字信号处理块（例如，转换为功能特定块）提供附加输入的专用路由互连，使得信号处理块接收附加信号。这些附加信号可以经由专用路由互连而被输入到信号处理块中，而不会显着增加硅区域昂贵的输入互连资源。

3. 发明授权

US07368944B1 Organizations of logic modules in programmable logic devices 有权
标题翻译：可编程逻辑器件中逻辑模块的组织
公开(公告)号：US07368944B1
公开(公告)日：2008-05-06
申请号：US11649748
申请日：2007-01-03
申请人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
发明人： Michael D. Hutton , Bruce Pedersen , Sinan Kaptanoglu , David Lewis , Tim Vanderhoek
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
摘要翻译：在可编程逻辑器件上的多个实例中使用的可编程逻辑元件组合包括多于共享次级信号（例如，时钟，时钟使能，清零等）选择电路的传统数量的逻辑元件。这种分组中的逻辑元素被划分为至少两个子组。提供了可编程互连电路，用于选择性地将分组外的信号和分组中的逻辑元件反馈的信号分组中的逻辑元件的主要输入。可编程互连电路将这些信号中的至少一些信号的可能应用限制到子组中的一个或另一个，并且/或提供这些信号中的至少一些信号到其中一个子组的较大百分比的主要输入的可能应用比对方。

4. 发明授权

US06747480B1 Programmable logic devices with bidirect ional cascades 有权
标题翻译：具有直接级联的可编程逻辑器件
公开(公告)号：US06747480B1
公开(公告)日：2004-06-08
申请号：US10195209
申请日：2002-07-12
申请人： Sinan Kaptanoglu , Michael D. Hutton , James Schleicher
发明人： Sinan Kaptanoglu , Michael D. Hutton , James Schleicher
IPC分类号： H03K19177
CPC分类号： H03K19/17748 , H03K19/1737 , H03K19/17736
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. The regions of logic may include logic subregions that each have a look-up table. Interconnection resources (e.g., inter-region and intra-region interconnection conductors, signal buffers and drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections between the look-up tables. Programmable bidirectional cascade circuitry that is distinct from the interconnections may be used to make connections directly from the output of one look-up table to another without using the interconnection resources. The programmable cascade circuitry may be programmed so that multiple look-up tables are interconnected to form sequential cascade chains or cascade trees.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。逻辑区域可以包括各自具有查找表的逻辑子区域。在设备上提供互连资源（例如，区域间和区域内互连导体，信号缓冲器和驱动器，可编程连接器等），用于在查找表之间进行可编程互连。与互连不同的可编程双向级联电路可用于使连接从一个查找表的输出直接连接到另一个查找表，而不使用互连资源。可编程级联电路可以被编程，使得多个查找表互连以形成顺序级联链或级联树。

5. 发明申请

US20130009666A1 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 审中-公开
标题翻译：具有集成应用的现场可编程阵列特殊集成电路布
公开(公告)号：US20130009666A1
公开(公告)日：2013-01-10
申请号：US13613925
申请日：2012-09-13
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

6. 发明授权

US08314636B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US08314636B2
公开(公告)日：2012-11-20
申请号：US12767696
申请日：2010-04-26
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

7. 发明申请

US20090051387A1 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US20090051387A1
公开(公告)日：2009-02-26
申请号：US11894283
申请日：2007-08-20
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

8. 发明授权

US08601424B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 有权
公开(公告)号：US08601424B1
公开(公告)日：2013-12-03
申请号：US12893904
申请日：2010-09-29
申请人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
发明人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.

9. 发明授权

US07890910B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 有权
标题翻译：可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器
公开(公告)号：US07890910B1
公开(公告)日：2011-02-15
申请号：US11499451
申请日：2006-08-04
申请人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
发明人： Michael D. Hutton , Gregg William Baeckler , Jinyong Yuan , Chris Wysocki , Pouyan Djahani
IPC分类号： G06F17/50
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译：具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。多个逻辑块中的每一个还包括一个或多个逻辑元件。逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

10. 发明授权

US07705628B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
标题翻译：可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器
公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
申请人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
发明人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译：具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。多个逻辑块中的每一个还包括一个或多个逻辑元件。逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

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