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1. 发明授权

US07368942B1 Dedicated resource interconnects 有权
标题翻译：专用资源互连
公开(公告)号：US07368942B1
公开(公告)日：2008-05-06
申请号：US11351882
申请日：2006-02-09
申请人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
发明人： Michael D. Hutton , Bruce B. Pedersen , James G. Schleicher, II
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17732
摘要： The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.
摘要翻译：本发明一般来说涉及利用与可编程逻辑器件中的数字信号处理块相邻的逻辑组的现有输出来扩展数字信号处理块的功能。来自逻辑组的输出被用作为数字信号处理块（例如，转换为功能特定块）提供附加输入的专用路由互连，使得信号处理块接收附加信号。这些附加信号可以经由专用路由互连而被输入到信号处理块中，而不会显着增加硅区域昂贵的输入互连资源。

2. 发明授权

US07724032B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US07724032B2
公开(公告)日：2010-05-25
申请号：US11894283
申请日：2007-08-20
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分电路。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分层组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

3. 发明申请

US20130009666A1 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 审中-公开
标题翻译：具有集成应用的现场可编程阵列特殊集成电路布
公开(公告)号：US20130009666A1
公开(公告)日：2013-01-10
申请号：US13613925
申请日：2012-09-13
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

4. 发明授权

US08314636B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US08314636B2
公开(公告)日：2012-11-20
申请号：US12767696
申请日：2010-04-26
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供具有集成专用集成电路（ASIC）结构的现场可编程门阵列（FPGA）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由自定义区域和接口区域组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

5. 发明申请

US20090051387A1 Field programmable gate array with integrated application specific integrated circuit fabric 有权
标题翻译：具有集成专用集成电路结构的现场可编程门阵列
公开(公告)号：US20090051387A1
公开(公告)日：2009-02-26
申请号：US11894283
申请日：2007-08-20
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。定制区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成到FPGA电路的其余部分。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

6. 发明授权

US09705506B2 Field programmable gate array with integrated application specific integrated circuit fabric 有权
公开(公告)号：US09705506B2
公开(公告)日：2017-07-11
申请号：US13613925
申请日：2012-09-13
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.

7. 发明申请

US20100207659A1 FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED APPLICATION SPECIFIC INTEGRATED CIRCUIT FABRIC 有权
标题翻译：具有集成应用的现场可编程阵列阵列集成电路布
公开(公告)号：US20100207659A1
公开(公告)日：2010-08-19
申请号：US12767696
申请日：2010-04-26
申请人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
发明人： Michael D. Hutton , James G. Schleicher, II , Daniel R. Mansur
IPC分类号： H03K19/177 , G06F17/50
CPC分类号： H03K19/17744 , H03K19/17732 , H03K19/17796
摘要： A field programmable gate array (“FPGA”) is provided having integrated application specific integrated circuit (“ASIC”) fabric. The ASIC fabric may be used to implement one or more custom or semi-custom hard blocks within the FPGA. The ASIC fabric can be made up of a “custom region” and an “interface region.” The custom region can implement the custom or semi-custom ASIC design and the interface region can integrate and connect the custom region to the rest of the FPGA circuitry. The custom region may be based on a structured ASIC design. The interface region may allow the ASIC fabric to be incorporated within the hierarchical organization of the FPGA, allowing the custom region to connect to the FPGA circuitry in a seamless manner.
摘要翻译：提供了具有集成专用集成电路（“ASIC”）结构的现场可编程门阵列（“FPGA”）。 ASIC结构可以用于在FPGA内实现一个或多个定制或半定制硬块。 ASIC结构可以由“自定义区域”和“接口区域”组成。自定义区域可以实现定制或半定制ASIC设计，接口区域可以将自定义区域集成并连接到FPGA的其余部分电路。定制区域可以基于结构化ASIC设计。接口区域可以允许将ASIC结构并入FPGA的分级组织中，从而允许定制区域以无缝的方式连接到FPGA电路。

8. 发明授权

US07420390B1 Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size 有权
标题翻译：用于在现场可编程门阵列中实现附加寄存器以减少设计尺寸的方法和装置
公开(公告)号：US07420390B1
公开(公告)日：2008-09-02
申请号：US11328407
申请日：2006-01-09
申请人： Michael D. Hutton , James G. Schleicher, II
发明人： Michael D. Hutton , James G. Schleicher, II
IPC分类号： H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728 , H03K19/17736 , H03K19/1776
摘要： A field programmable gate array includes a plurality of programmable logic blocks to implement one or more logic functions. The field programmable gate array includes a plurality of independent registers not associated with any specific one of the plurality of programmable logic blocks. The plurality of independent registers may be programmed to support any one of the plurality of programmable logic blocks.
摘要翻译：现场可编程门阵列包括多个可编程逻辑块以实现一个或多个逻辑功能。现场可编程门阵列包括不与多个可编程逻辑块中的任何特定的一个相关联的多个独立寄存器。多个独立寄存器可被编程为支持多个可编程逻辑块中的任何一个。

9. 发明授权

US08612772B1 Security core using soft key 有权
标题翻译：安全核心采用软键
公开(公告)号：US08612772B1
公开(公告)日：2013-12-17
申请号：US11490764
申请日：2006-07-20
申请人： Martin Langhammer , James G. Schleicher, II
发明人： Martin Langhammer , James G. Schleicher, II
IPC分类号： H04L9/32
CPC分类号： G06F21/76
摘要： Implementing a key and a protection circuit in a configurable device. A soft key associated with a protection circuit is combined with a user's electronic design in generating configuration data for download onto the configurable device. The placement and routing of the soft key is pseudo-randomly arranged with respect to the user's electronic design such that its placement and routing on the configurable device is substantially different for binary configuration data that is generated. Hiding the soft key and its connections to the protection circuit and assisting in protecting user electronic designs is achieved.
摘要翻译：在可配置设备中实现密钥和保护电路。与保护电路相关联的软键与用户的电子设计组合以产生用于下载到可配置设备上的配置数据。软键的放置和布线相对于用户的电子设计伪随机布置，使得其在可配置设备上的放置和布线对于生成的二进制配置数据而言是显着不同的。隐藏软键及其与保护电路的连接，并协助保护用户电子设计。

10. 发明授权

US07275232B2 Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits 有权
标题翻译：生产等效现场可编程门阵列和结构化专用集成电路的方法
公开(公告)号：US07275232B2
公开(公告)日：2007-09-25
申请号：US11097633
申请日：2005-04-01
申请人： James G. Schleicher, II , David Karchmer
发明人： James G. Schleicher, II , David Karchmer
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/505 , G06F2217/64
摘要： Compiler flows are provided that can produce functionally equivalent field programmable gate arrays (“FPGAs”) and structured application-specific integrated circuits (“structured ASICs”). The flows may include feeding back design transformations that are performed during either flow so that a later performance of the other flow will necessarily include the same transformations, thereby helping to ensure functional equivalence. The flows may include a comparison of intermediate results in order to prove that functional equivalence is being achieved.
摘要翻译：提供了可产生功能等同的现场可编程门阵列（“FPGA”）和结构化专用集成电路（“结构化ASIC”）的编译器流。流可以包括反馈在任一流程期间执行的设计变换，使得另一流程的稍后的性能将必然包括相同的变换，由此有助于确保功能等同性。流程可以包括中间结果的比较，以证明正在实现功能等同性。

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