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1. 发明授权

US07705628B1 Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers 失效
标题翻译：可编程逻辑器件具有具有专用硬件的逻辑元件，以将查找表配置为寄存器
公开(公告)号：US07705628B1
公开(公告)日：2010-04-27
申请号：US11486164
申请日：2006-07-12
申请人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
发明人： Michael D. Hutton , Andy L. Lee , Gregg William Baeckler , Jinyong Yuan , Keith Duwel
IPC分类号： G06F7/38 , H03K19/173 , H03K19/177 , H03K19/094 , H01L25/00
CPC分类号： H03K19/173 , H03K19/1736 , H03K19/17728
摘要： A programmable logic device architecture having logic elements with dedicated hardware to configure the look up tables of the logic element to either perform logic functions or to operate as a register for pipelining or other purposes. The programmable logic device includes a general interconnect and a plurality of logic array blocks interconnected by the general interconnect. Each of the plurality of logic blocks further includes one or more logic elements. The logic elements each include a first look up table, a second look up table, and dedicated hardware within the logic element to configure the first look table and the second look up table as a register without having to use the general interconnect. In one embodiment, the dedicated hardware includes a plurality of dedicated interconnects within the logic element to configure the two look up tables as a pair of cross coupled muxes or latches when configured as a register.
摘要翻译：具有逻辑元件的可编程逻辑器件结构具有专用硬件以配置逻辑元件的查找表以执行逻辑功能或作为流水线或其它目的的寄存器来操作。可编程逻辑器件包括通用互连和通过一般互连互连的多个逻辑阵列块。多个逻辑块中的每一个还包括一个或多个逻辑元件。逻辑元件各自包括第一查询表，第二查询表和逻辑元件内的专用硬件，以将第一查询表和第二查询表配置为寄存器而不必使用通用互连。在一个实施例中，专用硬件包括逻辑元件内的多个专用互连，以在配置为寄存器时将两个查找表配置为一对交叉耦合的多路复用器或锁存器。

2. 发明授权

US07902864B1 Heterogeneous labs 有权
标题翻译：异质实验室
公开(公告)号：US07902864B1
公开(公告)日：2011-03-08
申请号：US11292856
申请日：2005-12-01
申请人： Michael D. Hutton , Keith Duwel , Gregg William Baeckler
发明人： Michael D. Hutton , Keith Duwel , Gregg William Baeckler
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728
摘要： Disclosed is a programmable logic device (“PLD”) including at least one lookup table (“LUT”) based logic element (“LE”) of a first type and at least one LUT based LE of a second type. The first type of LE is different from the second type of LE. The term ‘different’ when used herein to describe the relationship of a first logic structure and/or its components to a second logic structure and/or its components indicates a difference in hardware design as opposed to a configuration difference or non-designed differences resulting, for example, from manufacturing variability. Additionally, a PLD can include at least one logic array block (“LAB”) of a first type having at least one LUT based LE and at least one LAB of a second type having at least one LUT based LE. The first type of LAB being different from the second type of LAB.
摘要翻译：公开了一种包括第一类型的至少一个查找表（“LUT”）逻辑元件（“LE”）和第二类型的至少一个基于LUT的LE的可编程逻辑器件（“PLD”）。 LE的第一种类型与第二种类型的LE不同。当用于描述第一逻辑结构和/或其组件与第二逻辑结构和/或其组件的关系时，术语“不同”表示硬件设计中的差异，而不是配置差异或非设计的差异，例如，从制造变异性。此外，PLD可以包括具有至少一个基于LUT的LE和具有至少一个基于LUT的LE的至少一个第二类型的至少一个LAB的第一类型的至少一个逻辑阵列块（“LAB”）。第一种类型的LAB与第二种类型的LAB不同。

3. 发明授权

US07733124B1 Method and apparatus for PLD having shared storage elements 有权
标题翻译：具有共享存储元件的PLD的方法和装置
公开(公告)号：US07733124B1
公开(公告)日：2010-06-08
申请号：US11766817
申请日：2007-06-22
申请人： Keith Duwel , Michael D. Hutton
发明人： Keith Duwel , Michael D. Hutton
IPC分类号： H03K19/177
CPC分类号： H03K19/17728
摘要： A programmable logic device (PLD) includes a core region having a plurality of logical array blocks (LABs). Each one of the plurality of logical array blocks include a plurality of logic elements capable of communicating with each other through interconnections defined within each logical array block. The logic elements include a look up table (LUT), wherein a LUT of a first logic element and a LUT of a second logic element share a register. In one embodiment, more than two logic elements may share a register. Thus, the embodiments provide for the ability to vary sequential logic, e.g., registers, instead of rigidly fixing the sequential logic and consequently the ratio of combinatorial logic to sequential logic.
摘要翻译：可编程逻辑器件（PLD）包括具有多个逻辑阵列块（LAB）的核心区域。多个逻辑阵列块中的每一个包括能够通过在每个逻辑阵列块内定义的互连而彼此通信的多个逻辑元件。逻辑元件包括查找表（LUT），其中第一逻辑元件的LUT和第二逻辑元件的LUT共享寄存器。在一个实施例中，多于两个逻辑元件可以共享寄存器。因此，这些实施例提供了改变顺序逻辑（例如，寄存器）的能力，而不是刚性地固定顺序逻辑，并且因此改变组合逻辑与顺序逻辑的比率。

4. 发明授权

US07287189B1 I/O configuration and reconfiguration trigger through testing interface 有权
标题翻译：通过测试界面进行I / O配置和重新配置触发
公开(公告)号：US07287189B1
公开(公告)日：2007-10-23
申请号：US10603888
申请日：2003-06-25
申请人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
发明人： Brian D. Johnson , Keith Duwel , Mario Guzman , Christopher F. Lane , Andy L. Lee
IPC分类号： G06F11/00
CPC分类号： G01R31/318572
摘要： A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection to a tester. A diagnostic controller in the device has a first mode for communicating the value on the I/O connection to the tester via the diagnostic interface, and a second mode for receiving an I/O configuration attribute value for the I/O connection from the diagnostic interface thereby modifying the configuration of the I/O connection. The device also includes a configuration controller that retrieves device configuration information from a configuration device in response to a signal. The signal can originate from an external source or from the diagnostic controller in response to a configuration instruction received via the diagnostic interface. The diagnostic interface may be a JTAG interface.
摘要翻译：可重构设备在测试期间从诊断接口加载I / O配置信息。该设备包括用于与其他设备通信值的可配置I / O连接。诊断接口将I / O连接的值传送给测试仪。设备中的诊断控制器具有用于经由诊断接口将I / O连接上的值传送给测试器的第一模式，以及用于从诊断接收I / O连接的I / O配置属性值的第二模式接口，从而修改I / O连接的配置。该设备还包括配置控制器，其响应于信号从配置设备检索设备配置信息。响应于通过诊断接口接收的配置指令，该信号可以来自外部源或诊断控制器。诊断接口可以是JTAG接口。

5. 发明授权

US07512849B1 Reconfigurable programmable logic system with configuration recovery mode 有权
标题翻译：具有配置恢复模式的可重构可编程逻辑系统
公开(公告)号：US07512849B1
公开(公告)日：2009-03-31
申请号：US11294715
申请日：2005-12-05
申请人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
发明人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
IPC分类号： G01R31/28 , G06F7/38
CPC分类号： G01R31/318516
摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.
摘要翻译：可编程逻辑系统包括可重新配置的可编程逻辑器件和存储至少两种配置的配置存储器。首先加载默认配置，然后加载所需的用户应用程序配置。如果用户应用程序配置失败，系统将保存有关故障的数据，然后返回到默认配置进行恢复。读取故障数据后，默认配置会导致调用操作员进行干预，或者在配置存储器中可用时加载不同的（例如，以前的）配置。该系统在用户可以远程更新配置的情况下特别有用。在另一种模式下，系统仅存储用户配置（首先被加载）和默认配置。如果新加载的配置失败，则加载默认配置，并向操作员发出信号，或者在加载不同配置时采取其他操作。

6. 发明授权

US07000161B1 Reconfigurable programmable logic system with configuration recovery mode 失效
公开(公告)号：US07000161B1
公开(公告)日：2006-02-14
申请号：US10270800
申请日：2002-10-11
申请人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
发明人： Tim Allen , Michael Fairman , Mario Guzman , Bryan Hoyer , Chris Lane , Kerry Veenstra , Keith Duwel , Andy L. Lee
IPC分类号： G01R31/28
CPC分类号： G01R31/318516
摘要： A programmable logic system includes a reconfigurable programmable logic device and configuration storage that stores at least two configurations. A default configuration loads first and then loads the desired user application configuration. If the user application configuration fails, the system saves data regarding the failure and then returns to the default configuration for recovery. The default configuration, after reading the failure data, causes an operator to be called to intervene, or loads a different (e.g., previous) configuration if one is available in configuration storage. The system is particularly useful where the user can update configurations remotely. In an alternative mode, the system stores only the user configuration (which is loaded first) and the default configuration. If a newly-loaded configuration fails, the default configuration is loaded and signals the operator or takes other action short of loading a different configuration.

7. 发明授权

US08554959B2 Apparatus and methods for communicating with programmable devices 有权
标题翻译：用于与可编程器件通信的装置和方法
公开(公告)号：US08554959B2
公开(公告)日：2013-10-08
申请号：US13461592
申请日：2012-05-01
申请人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
发明人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/10 , G06F17/5054 , H03K19/1776
摘要： A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.
摘要翻译：电路装置包括可编程逻辑器件。可编程逻辑器件包括配置逻辑电路。可编程逻辑器件还包括可配置互连。电路装置还包括被配置为向可编程逻辑器件提供数据的存储装置。存储装置经由双向接口与可编程逻辑装置进行通信。

8. 发明授权

US07702893B1 Integrated circuits with configurable initialization data memory addresses 失效
标题翻译：具有可配置初始化数据存储器地址的集成电路
公开(公告)号：US07702893B1
公开(公告)日：2010-04-20
申请号：US11525657
申请日：2006-09-22
申请人： Nicholas J. Rally , Dirk A. Reese , Keith Duwel
发明人： Nicholas J. Rally , Dirk A. Reese , Keith Duwel
IPC分类号： G06F15/177
CPC分类号： G06F9/4401
摘要： Systems and methods are provided for avoiding memory address conflicts in systems containing shared memory. Upon system power up, programmable logic device integrated circuits, microprocessors, and other integrated circuits with processing capabilities are provided with unique initialization data memory addresses. Each unique initialization data memory address corresponds to a respective non-overlapping block of memory in the shared memory. During initialization operations, the integrated circuits retrieve initialization data from the shared memory using the unique initialization data memory addresses. The integrated circuits can be organized using a master-slave architecture. The master can load the initialization data memory addresses into the slave integrated circuits using communications circuitry that is active after the slaves have powered up but before the slaves have been initialized.
摘要翻译：提供了系统和方法，用于避免包含共享内存的系统中的内存地址冲突。在系统上电时，可编程逻辑器件集成电路，微处理器和具有处理能力的其他集成电路提供唯一的初始化数据存储器地址。每个唯一的初始化数据存储器地址对应于共享存储器中相应的不重叠的存储器块。在初始化操作期间，集成电路使用唯一的初始化数据存储器地址从共享存储器检索初始化数据。可以使用主从架构来组织集成电路。主机可以使用通信电路将初始化数据存储器地址加载到从属集成电路中，这些通信电路在从机通电之后，但在从站已初始化之前处于活动状态。

9. 发明申请

US20080157813A1 APPARATUS AND METHODS FOR COMMUNICATING WITH PROGRAMMABLE LOGIC DEVICES 失效
公开(公告)号：US20080157813A1
公开(公告)日：2008-07-03
申请号：US12037935
申请日：2008-02-27
申请人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
发明人： Renxin Xia , Juju Chacko Joyce , Nitin Prasad , Kerry Veenstra , Keith Duwel
IPC分类号： H03K19/177
CPC分类号： G06F13/10 , G06F17/5054 , H03K19/1776
摘要： A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device configured to provide data to the programmable logic device. The storage device communicates with the programmable logic device via a bi-directional interface.

10. 发明授权

US09436250B1 Apparatus for improving power consumption of communication circuitry and associated methods 有权
标题翻译：用于改善通信电路和相关方法的功耗的装置
公开(公告)号：US09436250B1
公开(公告)日：2016-09-06
申请号：US13330635
申请日：2011-12-19
申请人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
发明人： Curt Wortman , Keith Duwel , Michael Menghui Zheng
IPC分类号： G06F1/00 , G06F1/32
CPC分类号： H03L7/0807 , G06F1/32 , G06F1/3278 , G06F1/3296 , G06F11/0736 , G06F11/076 , G06F11/079 , H03K19/0008 , H03K19/1737 , H03K19/17728 , H03K19/1776 , H04B17/309 , Y02D10/157
摘要： An integrated circuit (IC) includes communication circuitry, a body bias generator, and a controller. The communication circuitry includes a physical medium attachment (PMA) and a physical coding sublayer (PCS). The body bias generator provides body bias signals to the PMA and PCS. The controller controls the body bias generator such that the body bias signals are controlled to improve a power consumption of the communication circuitry.
摘要翻译：集成电路（IC）包括通信电路，体偏置发生器和控制器。通信电路包括物理介质连接（PMA）和物理编码子层（PCS）。身体偏置发生器向PMA和PCS提供身体偏置信号。控制器控制身体偏置发生器，使得身体偏置信号被控制以提高通信电路的功率消耗。

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