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1. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

2. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

3. 发明授权

US06829177B2 Output buffer for a nonvolatile memory with optimized slew-rate control 有权
标题翻译：具有优化的转换速率控制的非易失性存储器的输出缓冲器
公开(公告)号：US06829177B2
公开(公告)日：2004-12-07
申请号：US10161055
申请日：2002-05-30
申请人： Lorenzo Bedarida , Andrea Corradi , Maria Mostola , Massimo Zucchinali
发明人： Lorenzo Bedarida , Andrea Corradi , Maria Mostola , Massimo Zucchinali
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1051 , G11C16/26 , H03K19/01728
摘要： An output buffer includes an output stage formed by a pull-up transistor and a pull-down transistor connected in series between a supply line set at a supply potential and a ground line set at a ground potential. The output buffer further includes a pre-biasing stage for pre-biasing the control terminal of the pull-up transistor and a pre-biasing stage for pre-biasing the control terminal of the pull-down transistor in order to bring these transistors to the turning-on threshold.
摘要翻译：一个输出缓冲器包括一个由上拉晶体管形成的输出级和一个串联连接在一个设在电源电位的电源线和一个设在地电位的地线之间的下拉晶体管。输出缓冲器还包括用于预偏置上拉晶体管的控制端子的预偏置级和用于预偏压下拉晶体管的控制端的预偏置级，以便将这些晶体管导向开启门槛。

4. 发明申请

US20080170442A1 Column leakage compensation in a sensing circuit 有权
标题翻译：检测电路中的列泄漏补偿
公开(公告)号：US20080170442A1
公开(公告)日：2008-07-17
申请号：US11652828
申请日：2007-01-12
申请人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
发明人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

5. 发明授权

US07456678B2 Apparatus and method for providing a temperature compensated reference current 有权
标题翻译：用于提供温度补偿参考电流的装置和方法
公开(公告)号：US07456678B2
公开(公告)日：2008-11-25
申请号：US11548113
申请日：2006-10-10
申请人： Marco Passerini , Stefano Sivero , Mirella Marsella , Maria Mostola
发明人： Marco Passerini , Stefano Sivero , Mirella Marsella , Maria Mostola
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.
摘要翻译：公开了一种在电子设备中提供温度补偿参考电流的装置和方法。温度补偿参考电流补偿温度和其他电路变化。参考电流由改进的参考电流发生器提供，并且可以用在存储器件或任何其它期望的电路中。

6. 发明申请

US20080084240A1 APPARATUS AND METHOD FOR PROVIDING A TEMPERATURE COMPENSATED REFERENCE CURRENT 有权
标题翻译：提供温度补偿参考电流的装置和方法
公开(公告)号：US20080084240A1
公开(公告)日：2008-04-10
申请号：US11548113
申请日：2006-10-10
申请人： Marco Passerini , Stefano Sivero , Mirella Marsella , Maria Mostola
发明人： Marco Passerini , Stefano Sivero , Mirella Marsella , Maria Mostola
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： An apparatus and method for providing a temperature compensated reference current in an electronic device is disclosed. The temperature compensated reference current is compensated for temperature and other circuit variations. The reference current is provided by an improved reference current generator and may be used in a memory device or any other desired circuit.
摘要翻译：公开了一种在电子设备中提供温度补偿参考电流的装置和方法。温度补偿参考电流补偿温度和其他电路变化。参考电流由改进的参考电流发生器提供，并且可以用在存储器件或任何其它期望的电路中。

7. 发明授权

US07573748B2 Column leakage compensation in a sensing circuit 有权
标题翻译：检测电路中的列泄漏补偿
公开(公告)号：US07573748B2
公开(公告)日：2009-08-11
申请号：US11652828
申请日：2007-01-12
申请人： Lorenzo Bedarida , Maria Mostola , Davide Manfre' , Donato Ferrario
发明人： Lorenzo Bedarida , Maria Mostola , Davide Manfre' , Donato Ferrario
IPC分类号： G11C16/06
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

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