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1. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

2. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

3. 发明授权

US07249215B2 System for configuring parameters for a flash memory 有权
公开(公告)号：US07249215B2
公开(公告)日：2007-07-24
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.

4. 发明申请

US20140293707A1 Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices 有权
标题翻译：用于非易失性存储器件的擦除技术及其电路
公开(公告)号：US20140293707A1
公开(公告)日：2014-10-02
申请号：US14227676
申请日：2014-03-27
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/34
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

5. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

6. 发明申请

US20130016564A1 ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICES 失效
标题翻译：用于非易失性存储器件的擦除技术和电路
公开(公告)号：US20130016564A1
公开(公告)日：2013-01-17
申请号：US13181988
申请日：2011-07-13
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

7. 发明申请

US20080250191A1 FLEXIBLE, LOW COST APPARATUS AND METHOD TO INTRODUCE AND CHECK ALGORITHM MODIFICATIONS IN A NON-VOLATILE MEMORY 有权
标题翻译：灵活，低成本的设备和方法来引导和检查非易失性存储器中的算法修改
公开(公告)号：US20080250191A1
公开(公告)日：2008-10-09
申请号：US11696288
申请日：2007-04-04
申请人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
发明人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译：闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。微控制器耦合到命令用户界面。开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。

8. 发明授权

US07404049B2 Method and system for managing address bits during buffered program operations in a memory device 有权
标题翻译：用于在存储器件中缓存的程序操作期间管理地址位的方法和系统
公开(公告)号：US07404049B2
公开(公告)日：2008-07-22
申请号：US11123682
申请日：2005-05-06
申请人： Simone Bartoli , Stefano Surico , Davide Manfre′ , Donato Ferrario
发明人： Simone Bartoli , Stefano Surico , Davide Manfre′ , Donato Ferrario
IPC分类号： G06F12/00
CPC分类号： G06F12/04 , G11C16/10 , G11C2216/14
摘要： A method and system for managing a buffered program operation for plurality of words is described. In one aspect, the method and system include providing an internal buffer including a plurality of locations and at least one bit location for the plurality of locations. Each of the words is stored in a location of the plurality of locations. The words are associated with internal address bits for the locations. At least one of the internal address bits is at least one group address bit that corresponds to all of the words. A remaining portion of the internal address bits is associated at least one of the words. The at least one bit location stores the at least one group address bit for the words. Thus, in one aspect, the method and system include storing each of the words one of the buffer locations. The method and system also include associating the at least one group address bit with the buffer location for each of the words.
摘要翻译：描述用于管理用于多个单词的缓冲程序操作的方法和系统。一方面，该方法和系统包括提供包括多个位置的多个位置和至少一个位置的内部缓冲器。每个词都存储在多个位置的位置。这些单词与位置的内部地址位相关联。至少一个内部地址位是与所有字对应的至少一个组地址位。内部地址位的剩余部分与至少一个字相关联。所述至少一个位位置存储所述字的至少一个组地址位。因此，在一个方面，该方法和系统包括将每个单词存储在缓冲器位置之一中。该方法和系统还包括将至少一个组地址位与每个字的缓冲器位置相关联。

9. 发明申请

US20080165585A1 ERASE VERIFY METHOD FOR NAND-TYPE FLASH MEMORIES 有权
标题翻译：用于NAND型闪存存储器的擦除验证方法
公开(公告)号：US20080165585A1
公开(公告)日：2008-07-10
申请号：US11619978
申请日：2007-01-04
申请人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
发明人： Stefano Surico , Marco Passerini , Fabio Tassan Caser , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/344 , G11C16/0483
摘要： An erase-verify method for a NAND flash memory includes a serial double-step erase verify. A verify operation is performed on cells in the unit connected to even word lines by biasing all the even word lines at the read voltage value used in read mode, and by biasing all the odd word lines at the pass voltage value used in read mode of the selected unit. A verify operation is performed on the cells connected to odd word lines by biasing all the odd word lines at the read voltage value used in read mode and by biasing the all even word lines at the pass voltage value used in read mode of the selected unit. Verifying the odd and even word lines may be performed in either order.
摘要翻译： NAND闪存的擦除验证方法包括串行双步擦除验证。通过在读取模式下使用的读取电压值偏置所有偶数字线，并且通过在读取模式中使用的通过电压值偏置所有奇数字线，对连接到偶数字线的单元中的单元执行验证操作所选单位。通过在读取模式中使用的读取电压值偏置所有奇数字线并且通过在所选择的单元的读取模式中使用的通过电压值偏置所有偶数字线来对连接到奇数字线的单元执行验证操作。验证奇数和偶数字线可以以任何顺序执行。

10. 发明申请

US20070083699A1 System for configuring parameters for a flash memory 有权
标题翻译：用于配置闪存的参数的系统
公开(公告)号：US20070083699A1
公开(公告)日：2007-04-12
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.
摘要翻译：用于配置闪存设备中使用的参数的系统。从存储器检索加载指令和相关联的地址，并且该地址用于选择存储配置值的配置寄存器。配置值加载到相关联的专用寄存器，以在闪存操作中配置闪存的参数。

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