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1. 发明申请

US20080170442A1 Column leakage compensation in a sensing circuit 有权
标题翻译：检测电路中的列泄漏补偿
公开(公告)号：US20080170442A1
公开(公告)日：2008-07-17
申请号：US11652828
申请日：2007-01-12
申请人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
发明人： Lorenzo Bedarida , Maria Mostola , Davide Manfre , Donato Ferrario
IPC分类号： G11C16/28 , G11C7/06 , G11C29/00
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

2. 发明授权

US07573748B2 Column leakage compensation in a sensing circuit 有权
标题翻译：检测电路中的列泄漏补偿
公开(公告)号：US07573748B2
公开(公告)日：2009-08-11
申请号：US11652828
申请日：2007-01-12
申请人： Lorenzo Bedarida , Maria Mostola , Davide Manfre' , Donato Ferrario
发明人： Lorenzo Bedarida , Maria Mostola , Davide Manfre' , Donato Ferrario
IPC分类号： G11C16/06
CPC分类号： G11C29/12 , G11C7/062 , G11C7/12 , G11C16/04 , G11C16/26
摘要： A sensing circuit. In one embodiment, the sensing circuit includes a memory circuit including a first bitline that sinks a first leakage current, a compensation device coupled to the memory circuit, and a compensation circuit coupled to the compensation device. The compensation circuit includes a second bitline that sinks a second leakage current that matches the first leakage current. The compensation device is operative to compensate the first leakage current through a current based on the second leakage current. According to the system and method disclosed herein, the compensation device and compensation circuit prevents errors when determining the state of the memory cell.
摘要翻译：感测电路。在一个实施例中，感测电路包括存储电路，其包括吸收第一泄漏电流的第一位线，耦合到存储器电路的补偿装置以及耦合到补偿装置的补偿电路。补偿电路包括吸收与第一泄漏电流匹配的第二漏电流的第二位线。补偿装置用于基于第二泄漏电流补偿通过电流的第一泄漏电流。根据本文公开的系统和方法，在确定存储单元的状态时，补偿装置和补偿电路可以防止错误。

3. 发明授权

US06734701B2 Fast controlled output buffer 有权
标题翻译：快速控制输出缓冲器
公开(公告)号：US06734701B2
公开(公告)日：2004-05-11
申请号：US10323614
申请日：2002-12-18
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： H03K1716
CPC分类号： H03K17/166 , H03K17/165 , H03K19/00361
摘要： An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor. The discharge current control circuit preferably includes a discharge resistor and a mirrored current transistor feedback controlled by an output capacitor.
摘要翻译：输出缓冲器接通控制电路包括多个晶体管和放电电流控制电路。第一晶体管具有连接到内部电压线并由输出数据源控制的第一端子。第二晶体管具有连接到内部电压线的第一端子，并由第一晶体管的第二端子控制。第二晶体管还具有连接到输出电容器的第一端子的第二端子。第三晶体管由输出数据源控制，并具有连接到公共电压的第一端子。数字控制第四晶体管，并且具有连接到第二晶体管的第二端子的第一端子。第四晶体管还具有连接到公共电压的第二端子。放电电流控制电路优选地被主动地控制并且连接在第一晶体管的第二端子和第三晶体管的第二端子之间。放电电流控制电路优选地包括放电电阻器和由输出电容器控制的镜像电流晶体管反馈。

4. 发明申请

US20100149896A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20100149896A1
公开(公告)日：2010-06-17
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/06 , H03K5/24
CPC分类号： G11C7/062
摘要： A sense amplifier comprises a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

5. 发明授权

US07499334B2 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US07499334B2
公开(公告)日：2009-03-03
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

6. 发明申请

US20080170454A1 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

7. 发明申请

US20070047325A1 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US20070047325A1
公开(公告)日：2007-03-01
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre
IPC分类号： G11C16/06
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

8. 发明授权

US06794927B2 Modular charge pump architecture 有权
标题翻译：模块化电荷泵结构
公开(公告)号：US06794927B2
公开(公告)日：2004-09-21
申请号：US10328911
申请日：2002-12-24
申请人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
发明人： Lorenzo Bedarida , Stefano Sivero , Davide Manfre
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/077
摘要： An voltage regulation apparatus for generating a supply voltage internally within an integrated circuit with a modular arrangement of charge pumps. The charge pumps feature a first plurality of parallel-connected blocks of charge pump stages including a first block of charge pump stages, a last block of charge pump stages, and at least one intermediate block of charge pump stages therebetween. Each of the parallel-connected blocks of charge pump stages includes a group of a second plurality of charge pump stages cascade-connected in series; and an output stage connected to an output node. Desired output voltages are obtained by using combinatorial clock signals, generated by a logic circuit, directed to the various charge pump stages.
摘要翻译：一种电压调节装置，用于在具有电荷泵的模块化布置的集成电路内部产生电源电压。电荷泵具有第一多个并联连接的电荷泵级的块，包括电荷泵级的第一级，电荷泵级的最后一级，以及其间的至少一个中间电荷泵级。电荷泵级的每个并联连接的块包括串联级联的第二组多个电荷泵级的组; 以及连接到输出节点的输出级。通过使用由逻辑电路产生的组合时钟信号来获得期望的输出电压，指向各种电荷泵级。

9. 发明授权

US06829177B2 Output buffer for a nonvolatile memory with optimized slew-rate control 有权
标题翻译：具有优化的转换速率控制的非易失性存储器的输出缓冲器
公开(公告)号：US06829177B2
公开(公告)日：2004-12-07
申请号：US10161055
申请日：2002-05-30
申请人： Lorenzo Bedarida , Andrea Corradi , Maria Mostola , Massimo Zucchinali
发明人： Lorenzo Bedarida , Andrea Corradi , Maria Mostola , Massimo Zucchinali
IPC分类号： G11C1604
CPC分类号： G11C7/1057 , G11C7/1051 , G11C16/26 , H03K19/01728
摘要： An output buffer includes an output stage formed by a pull-up transistor and a pull-down transistor connected in series between a supply line set at a supply potential and a ground line set at a ground potential. The output buffer further includes a pre-biasing stage for pre-biasing the control terminal of the pull-up transistor and a pre-biasing stage for pre-biasing the control terminal of the pull-down transistor in order to bring these transistors to the turning-on threshold.
摘要翻译：一个输出缓冲器包括一个由上拉晶体管形成的输出级和一个串联连接在一个设在电源电位的电源线和一个设在地电位的地线之间的下拉晶体管。输出缓冲器还包括用于预偏置上拉晶体管的控制端子的预偏置级和用于预偏压下拉晶体管的控制端的预偏置级，以便将这些晶体管导向开启门槛。

10. 发明授权

US07920436B2 Sense amplifier 有权
标题翻译：感应放大器
公开(公告)号：US07920436B2
公开(公告)日：2011-04-05
申请号：US12336965
申请日：2008-12-17
申请人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
发明人： Lorenzo Bedarida , Simone Bartoli , Davide Manfre , Alex Pojer
IPC分类号： G11C7/00
CPC分类号： G11C7/062
摘要： A sense amplifier includes a first cascode transistor, a second cascode transistor, a first feedback circuit, a second feedback circuit, and a comparator. The drain of the first cascode transistor is connected directly to a first voltage source. The gate of the first cascode transistor is connected to the first feedback circuit and a first input of the comparator, and the source of the first cascode transistor is connected to the first feedback circuit and a first column decoder. The drain of the second cascode transistor is connected directly to a second voltage source. The gate of the second cascode transistor is connected to the second feedback circuit and a second input of the comparator, and the source of the second cascode transistor is connected to the second feedback circuit and a second column decoder.
摘要翻译：读出放大器包括第一共源共栅晶体管，第二共源共栅晶体管，第一反馈电路，第二反馈电路和比较器。第一共源共栅晶体管的漏极直接连接到第一电压源。第一共源共栅晶体管的栅极连接到第一反馈电路和比较器的第一输入端，并且第一共源共栅晶体管的源极连接到第一反馈电路和第一列解码器。第二共源共栅晶体管的漏极直接连接到第二电压源。第二共源共栅晶体管的栅极连接到第二反馈电路和比较器的第二输入端，第二共源共栅晶体管的源极连接到第二反馈电路和第二列解码器。

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