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1. 发明授权

US06743727B2 Method of etching high aspect ratio openings 失效
标题翻译：蚀刻高纵横比开口的方法
公开(公告)号：US06743727B2
公开(公告)日：2004-06-01
申请号：US09874109
申请日：2001-06-05
申请人： Gangadhara S. Mathad , Siddhartha Panda , Rajiv M. Ranade
发明人： Gangadhara S. Mathad , Siddhartha Panda , Rajiv M. Ranade
IPC分类号： H01L2100
CPC分类号： H01L21/30655 , H01L21/3065 , H01L21/3081 , H01L21/76224
摘要： A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.
摘要翻译：在硅衬底中蚀刻深，高纵横比开口的方法包括使用包含含溴气体，含氧气体和第一含氟气体的第一气体混合物形成的第一等离子体蚀刻衬底。用第一气体混合物的蚀刻工艺产生侧壁钝化沉积物，其沉积在开口入口附近。为了减少这种积累并且为了提高平均蚀刻速率，通过使用含有硅烷和第二含氟气体的混合物形成第二等离子体来周期性地减薄侧壁钝化沉积物。在整个工艺期间，衬底保持在相同的等离子体反应器室中，并且在稀化步骤期间连续维持等离子体。可以使用重复的蚀刻和变薄循环来产生大于40倍宽度的孔。

2. 发明授权

US06709917B2 Method to increase the etch rate and depth in high aspect ratio structure 失效
标题翻译：在高纵横比结构中增加蚀刻速率和深度的方法
公开(公告)号：US06709917B2
公开(公告)日：2004-03-23
申请号：US10145230
申请日：2002-05-13
申请人： Siddhartha Panda , Rajiv M. Ranade , Gangadhara S. Mathad
发明人： Siddhartha Panda , Rajiv M. Ranade , Gangadhara S. Mathad
IPC分类号： H01L218242
CPC分类号： H01L27/1087 , H01L21/3065
摘要： A method of fabricating a high aspect ratio deep trench in a semiconductor substrate comprising reducing the formation of a passivation film during the etching of the trench by including a first step of contacting the substrate in which the deep trench is to be formed with a fluorine poor or low concentration of a fluorine gas in the plasma of etchant gases for etching the high aspect ratio deep trench, followed by a second step of increasing the concentration of the fluorine containing gas to create a fluorine-rich plasma while lowering the chamber pressure of the reactor and RF power. Preferably, the second step is introduced periodically during the etching of a deep trench in an alternating manner.
摘要翻译：一种在半导体衬底中制造高深宽比深沟槽的方法，包括在蚀刻蚀刻期间减少钝化膜的形成，包括使要形成深沟槽的衬底与氟差的接触的第一步骤或低浓度的蚀刻剂气体等离子体中的氟气，用于蚀刻高纵横比深沟槽，随后是增加含氟气体的浓度以产生富氟等离子体同时降低室内压力的第二步骤电抗器和RF功率。优选地，在以交替方式蚀刻深沟槽期间周期性地引入第二步骤。

3. 发明授权

US07687829B2 Stressed field effect transistors on hybrid orientation substrate 失效
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07687829B2
公开(公告)日：2010-03-30
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

4. 发明申请

US20080179627A1 Strained MOS devices using source/drain epitaxy 有权
标题翻译：使用源极/漏极外延的应变MOS器件
公开(公告)号：US20080179627A1
公开(公告)日：2008-07-31
申请号：US11669902
申请日：2007-01-31
申请人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
发明人： Meikei Ieong , Xiao Hu Liu , Qiqing Christine Ouyang , Siddhartha Panda , Haizhou Yin
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848 , H01L29/78687
摘要： NMOS and PMOS device structures with separately strained channel regions and methods of their fabrication are disclosed. The source and the drain of the NMOS device is epitaxially grown of a material which causes a shift in the strain of the NMOS device channel in the tensile direction. While, the source and the drain of the PMOS device is epitaxially grown of a material which causes a shift in the strain of the PMOS device channel in the compressive direction.
摘要翻译：公开了具有单独应变通道区域的NMOS和PMOS器件结构及其制造方法。 NMOS器件的源极和漏极由引起NMOS器件沟道在拉伸方向上的应变移动的材料外延生长。而PMOS器件的源极和漏极是外延生长的，这种材料导致PMOS器件沟道在压缩方向上的应变移动。

5. 发明申请

US20080090370A1 Post-silicide spacer removal 失效
公开(公告)号：US20080090370A1
公开(公告)日：2008-04-17
申请号：US11548870
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Siddhartha Panda , Yong Meng Lee
IPC分类号： H01L21/331
CPC分类号： H01L21/32 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A method forms a gate conductor over a substrate, forms spacers (e.g., nitride spacers) on sides of the gate conductor, and implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers. Then the method forms a silicide on surfaces of the exposed regions of the substrate. The method forms a conformal protective layer (e.g., an oxide or other similar material) over the silicide, the spacers, and the gate conductor. Next, the method forms a non-conformal sacrificial layer (e.g., nitride or other material that can be selectively removed with respect to the protective layer) over the protective layer. A subsequent partial etching process partially etches the sacrificial layer such that relatively thinner regions of the sacrificial layer that are over the spacers are completely removed and the relatively thicker regions of the sacrificial layer that are over the substrate are not removed. The next step in the method removes only those portions of the protective layer that cover the spacers, without removing the portions of the protective layer that cover the silicide. As the spacers are now exposed and the silicide is protected by the protective and sacrificial layers, the method can safely remove the spacers without affecting the silicide.

6. 发明申请

US20070293016A1 SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LINEWIDTH AND METHOD FOR FABRICATION THEROF 审中-公开
标题翻译：包括具有可变线性的分离区域的半导体结构及其制造方法
公开(公告)号：US20070293016A1
公开(公告)日：2007-12-20
申请号：US11424076
申请日：2006-06-14
申请人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
发明人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
IPC分类号： H01L21/76
CPC分类号： H01L21/823892 , H01L21/76218 , H01L21/76232 , H01L21/823878
摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.
摘要翻译：半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。半导体结构还包括位于掺杂区和外延区的最后隔离区。最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。制造半导体结构的方法提供了在外延区之前形成掺杂区。掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

7. 发明申请

US20070056930A1 POLYSILICON ETCHING METHODS 审中-公开
标题翻译：多晶硅蚀刻方法
公开(公告)号：US20070056930A1
公开(公告)日：2007-03-15
申请号：US11162550
申请日：2005-09-14
申请人： Seiji Iseda , Siddhartha Panda , Michael Sievers , Richard Wise
发明人： Seiji Iseda , Siddhartha Panda , Michael Sievers , Richard Wise
IPC分类号： C03C25/68 , B44C1/22 , H01L21/461 , C23F1/00
CPC分类号： H01L21/32137
摘要： Polysilicon etching methods are disclosed that employ a gas flow including perfluorocyclopentene (C5F8) and nitrogen trifluoride (NF3). The etching methods achieved a substantially vertical profile and smoother surfaces, and may achieve a 3sigma variation as low as 3.0 nm.
摘要翻译：公开了采用包括全氟环戊烯（C 5 H 5 F 8 N）和三氟化氮（NF 3 3））的气流的多晶硅蚀刻方法。蚀刻方法实现了基本垂直的轮廓和更平滑的表面，并且可以实现低至3.0nm的3σ变化。

8. 发明申请

US20070048980A1 METHOD FOR POST-RIE PASSIVATION OF SEMICONDUCTOR SURFACES FOR EPITAXIAL GROWTH 审中-公开
标题翻译：用于剥离外延生长的半导体表面的方法
公开(公告)号：US20070048980A1
公开(公告)日：2007-03-01
申请号：US11161964
申请日：2005-08-24
申请人： Judson Holt , Siddhartha Panda
发明人： Judson Holt , Siddhartha Panda
IPC分类号： H01L21/20 , H01L21/302
CPC分类号： H01L21/02057 , H01L21/02367 , H01L21/02499 , H01L21/02518 , H01L21/02658
摘要： A method for preparing a substrate for epitaxial crystal growth thereon includes performing a reactive ion etch (RIE) on a selected area of the substrate to be prepared for epitaxial crystal growth, discontinuing the introduction of an etchant species associated with the RIE, and introducing a monolayer forming species into a chamber containing the substrate. The neutral species is selected so as to form a passivating monolayer on the selected area of the substrate, wherein the monolayer is resistant to the formation of native oxide thereon.
摘要翻译：制备用于外延晶体生长的衬底的方法包括在待制备用于外延晶体生长的衬底的选定区域上执行反应离子蚀刻（RIE），停止引入与RIE相关联的蚀刻剂物质，并引入单层形成物质进入含有底物的室。选择中性物质以在底物的选定区域上形成钝化单层，其中单层对其上形成天然氧化物具有抗性。

9. 发明授权

US07087532B2 Formation of controlled sublithographic structures 失效
标题翻译：形成受控亚光刻结构
公开(公告)号：US07087532B2
公开(公告)日：2006-08-08
申请号：US10711683
申请日：2004-09-30
申请人： David M Dobuzinsky , Jochen C. Beintner , Siddhartha Panda
发明人： David M Dobuzinsky , Jochen C. Beintner , Siddhartha Panda
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/3088 , H01L21/32139 , H01L29/66795 , H01L29/785
摘要： A process for forming sublithographic structures such as fins employs a hardmask protective layer above a hardmask to absorb damage during a dry etching step, thereby preserving symmetry in the hardmask and eliminating a source of defects.
摘要翻译：用于形成诸如翅片之类的亚光刻结构的工艺使用硬掩模上方的硬掩模保护层来在干蚀刻步骤期间吸收损伤，由此保持硬掩模中的对称性并消除缺陷源。

10. 发明申请

US20060065914A1 STRUCTURE AND METHOD FOR MAKING STRAINED CHANNEL FIELD EFFECT TRANSISTOR USING SACRIFICIAL SPACER 有权
公开(公告)号：US20060065914A1
公开(公告)日：2006-03-30
申请号：US10711637
申请日：2004-09-29
申请人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
发明人： Huajie Chen , Dureseti Chidambarrao , Sang-Hyun Oh , Siddhartha Panda , Werner Rausch , Tsutomu Sato , Henry Utomo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28052 , H01L21/28079 , H01L21/7624 , H01L29/1045 , H01L29/165 , H01L29/4933 , H01L29/495 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

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