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1. 发明申请

US20070293016A1 SEMICONDUCTOR STRUCTURE INCLUDING ISOLATION REGION WITH VARIABLE LINEWIDTH AND METHOD FOR FABRICATION THEROF 审中-公开
标题翻译：包括具有可变线性的分离区域的半导体结构及其制造方法
公开(公告)号：US20070293016A1
公开(公告)日：2007-12-20
申请号：US11424076
申请日：2006-06-14
申请人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
发明人： Zhijiong Luo , Hung Y. Ng , Nivo Rovedo , Phung T. Nguyen , William C. Wille , Richard Lindsay , Zhao Lun , Yung Fu Chong , Siddhartha Panda
IPC分类号： H01L21/76
CPC分类号： H01L21/823892 , H01L21/76218 , H01L21/76232 , H01L21/823878
摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.
摘要翻译：半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。半导体结构还包括位于掺杂区和外延区的最后隔离区。最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。制造半导体结构的方法提供了在外延区之前形成掺杂区。掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

2. 发明申请

US20080283934A1 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 有权
标题翻译：用于接触的大量L型硅胶和相关方法
公开(公告)号：US20080283934A1
公开(公告)日：2008-11-20
申请号：US12182212
申请日：2008-07-30
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L29/78 , H01L21/44
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

3. 发明授权

US07442619B2 Method of forming substantially L-shaped silicide contact for a semiconductor device 有权
标题翻译：形成用于半导体器件的基本上L形硅化物接触的方法
公开(公告)号：US07442619B2
公开(公告)日：2008-10-28
申请号：US11383965
申请日：2006-05-18
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L21/283 , H01L23/482
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a substantially L-shaped silicide element forming a contact is disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the substantially L-shaped silicide element includes a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了一种制造具有形成接触的大致L形硅化物元件的半导体器件的方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，基本上L形的硅化物元件包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触 STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

4. 发明授权

US08643119B2 Substantially L-shaped silicide for contact 有权
标题翻译：基本上L型硅化物进行接触
公开(公告)号：US08643119B2
公开(公告)日：2014-02-04
申请号：US12182212
申请日：2008-07-30
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure for a semiconductor device, according to an embodiment, includes: a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element.
摘要翻译：根据实施例的用于半导体器件的结构包括：基本上L形的硅化物元件，其包括基底构件和延伸构件，其中所述基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基部构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。

5. 发明申请

US20070267753A1 SUBSTANTIALLY L-SHAPED SILICIDE FOR CONTACT AND RELATED METHOD 有权
标题翻译：用于接触的大量L型硅胶和相关方法
公开(公告)号：US20070267753A1
公开(公告)日：2007-11-22
申请号：US11383965
申请日：2006-05-18
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Hung Y. Ng , Kern Rim , Nivo Rovedo
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/823814 , H01L21/823871 , H01L21/823878 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.
摘要翻译：公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

6. 发明授权

US07442618B2 Method to engineer etch profiles in Si substrate for advanced semiconductor devices 有权
标题翻译：在先进半导体器件的Si衬底中设计蚀刻轮廓的方法
公开(公告)号：US07442618B2
公开(公告)日：2008-10-28
申请号：US11182682
申请日：2005-07-16
申请人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
发明人： Yung Fu Chong , Brian Joseph Greene , Siddhartha Panda , Nivo Rovedo
IPC分类号： H01L21/44
CPC分类号： H01L29/7833 , H01L21/76232 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/7846 , H01L29/7848
摘要： Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.
摘要翻译：示出了用于形成用于隔离和/或应力衬底的键孔区域的结构和方法。在第一实施例中，我们在第一开口中的衬底中形成倒置的键孔形沟槽，优选地使用两步蚀刻。接下来，我们使用在倒置的键孔沟槽的侧壁上绝缘和/或产生应力的材料填充倒置的孔眼沟槽。在第二实施例中，我们形成与栅极和隔离结构相邻的键孔应力区域。键孔应力区域在FET的通道区域附近产生应力，以提高FET性能。应力区域可以用绝缘体或半导体材料填充。

7. 发明授权

US07566609B2 Method of manufacturing a semiconductor structure 失效
标题翻译：制造半导体结构的方法
公开(公告)号：US07566609B2
公开(公告)日：2009-07-28
申请号：US11164568
申请日：2005-11-29
申请人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
发明人： Zhijiong Luo , Yung Fu Chong , Huilong Zhu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823835 , H01L21/823842 , H01L21/823864 , H01L29/4975 , H01L29/66545 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.
摘要翻译：提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。栅极结构包括栅极电介质层，导电层和绝缘层。形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。还提供了一种FET器件。

8. 发明授权

US08912567B2 Strained channel transistor and method of fabrication thereof 有权
标题翻译：应变通道晶体管及其制造方法
公开(公告)号：US08912567B2
公开(公告)日：2014-12-16
申请号：US12852995
申请日：2010-08-09
申请人： Yung Fu Chong , Zhijiong Luo , Judson Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson Holt
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/66628 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66636
摘要： The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.
摘要翻译：本发明涉及半导体集成电路。更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

9. 发明申请

US20080286916A1 METHODS OF STRESSING TRANSISTOR CHANNEL WITH REPLACED GATE 审中-公开
标题翻译：用更换门压制晶体管通道的方法
公开(公告)号：US20080286916A1
公开(公告)日：2008-11-20
申请号：US12179042
申请日：2008-07-24
申请人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L. Tessier
发明人： Zhijiong Luo , Huilong Zhu , Yung Fu Chong , Brian L. Tessier
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/66545 , H01L29/78 , H01L29/7843 , H01L29/7845
摘要： Methods of stressing a channel of a transistor with a replaced gate and related structures are disclosed. A method may include providing an intrinsically stressed material over the transistor including a gate thereof; removing a portion of the intrinsically stressed material over the gate; removing at least a portion of the gate, allowing stress retained by the gate to be transferred to the channel; replacing (or refilling) the gate with a replacement gate; and removing the intrinsically stressed material. Removing and replacing the gate allows stress retained by the original gate to be transferred to the channel, with the replacement gate maintaining (memorizing) that situation. The methods do not damage the gate dielectric.
摘要翻译：公开了用替换的栅极和相关结构来施加晶体管的沟道的方法。一种方法可以包括在包括其栅极的晶体管上提供固有应力的材料; 在门上移除一部分本征应力材料; 去除栅极的至少一部分，允许由栅极保持的应力传递到通道; 用更换的门更换（或补充）门; 并去除本征应力材料。拆卸和更换门允许原始闸门保持的应力传递到通道，替换闸门保持（记住）这种情况。这些方法不会损坏栅极电介质。

10. 发明申请

US20080116482A1 METHOD TO FORM SELECTIVE STRAINED SI USING LATERAL EPITAXY 有权
标题翻译：使用侧向外延形成选择性应变的方法
公开(公告)号：US20080116482A1
公开(公告)日：2008-05-22
申请号：US11561982
申请日：2006-11-21
申请人： Yung Fu Chong , Zhijiong Luo , Judson R. Holt
发明人： Yung Fu Chong , Zhijiong Luo , Judson R. Holt
IPC分类号： H01L27/092 , H01L29/778 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/0653 , H01L29/66621 , H01L29/66636 , H01L29/66651 , H01L29/7833 , H01L29/7846 , H01L29/7848 , H01L29/78639
摘要： Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.
摘要翻译：通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。在第三示例性实施例中，形成PFET和NFET器件。在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。

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