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1. 发明授权

US07687829B2 Stressed field effect transistors on hybrid orientation substrate 失效
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07687829B2
公开(公告)日：2010-03-30
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

2. 发明申请

US20080251817A1 STRESSED FIELD EFFECT TRANSISTORS ON HYBRID ORIENTATION SUBSTRATE 失效
标题翻译：混合定向衬底上的应力场效应晶体管
公开(公告)号：US20080251817A1
公开(公告)日：2008-10-16
申请号：US12144250
申请日：2008-06-23
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造它们的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

3. 发明授权

US07863197B2 Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modification 有权
标题翻译：形成用于电荷载流子迁移率改变的横截面沙漏形通道区域的方法
公开(公告)号：US07863197B2
公开(公告)日：2011-01-04
申请号：US11306721
申请日：2006-01-09
申请人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing C. Ouyang , Siddhartha Panda
发明人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing C. Ouyang , Siddhartha Panda
IPC分类号： H01L21/302 , H01L21/00
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.
摘要翻译：制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。应力施加层位于沟道区附近。沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

4. 发明授权

US07405436B2 Stressed field effect transistors on hybrid orientation substrate 有权
标题翻译：混合取向衬底上强调场效应晶体管
公开(公告)号：US07405436B2
公开(公告)日：2008-07-29
申请号：US11029797
申请日：2005-01-05
申请人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Oiging C. Ouyang , Siddhartha Panda
发明人： Dureseti Chidambarrao , Judson R. Holt , Meikei Ieong , Oiging C. Ouyang , Siddhartha Panda
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L29/045 , H01L21/823807 , H01L29/7843
摘要： A semiconductor structure having improved carrier mobility is provided. The semiconductor structures includes a hybrid oriented semiconductor substrate having at least two planar surfaces of different crystallographic orientation, and at least one CMOS device located on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel. The present invention also provides methods of fabricating the same. In general terms, the inventive method includes providing a hybrid oriented substrate having at least two planar surfaces of different crystallographic orientation, and forming at least one CMOS device on each of the planar surfaces of different crystallographic orientation, wherein each CMOS device has a stressed channel.
摘要翻译：提供了具有改进的载流子迁移率的半导体结构。半导体结构包括具有不同晶体取向的至少两个平坦表面的混合取向半导体衬底，以及位于不同结晶取向的每个平面上的至少一个CMOS器件，其中每个CMOS器件具有应力通道。本发明还提供了制造该方法的方法。一般来说，本发明的方法包括提供具有至少两个具有不同晶体取向的平面表面的混合取向衬底，以及在不同结晶取向的每个平面上形成至少一个CMOS器件，其中每个CMOS器件具有受压沟道。

5. 发明申请

US20080258180A1 CROSS-SECTION HOURGLASS SHAPED CHANNEL REGION FOR CHARGE CARRIER MOBILITY MODIFICATION 有权
标题翻译：交叉部分HOURGLASS形状的通道区域用于充电载波移动性修改
公开(公告)号：US20080258180A1
公开(公告)日：2008-10-23
申请号：US11306721
申请日：2006-01-09
申请人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing Ouyang , Siddhartha Panda
发明人： Huajie Chen , Dureseti Chidambarrao , Judson R. Holt , Qiqing Ouyang , Siddhartha Panda
IPC分类号： H01L29/78 , H01L29/04 , H01L21/336
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A semiconductor structure and a method for fabricating the semiconductor structure include a semiconductor substrate having a cross-section hourglass shaped channel region. A stress imparting layer is located adjacent the channel region. The hourglass shape may provide for enhanced vertical tensile stress within the channel region when it is longitudinally compressive stressed by the stress imparting layer.
摘要翻译：半导体结构和制造半导体结构的方法包括具有横截面沙漏形沟道区域的半导体衬底。应力施加层位于沟道区附近。沙漏形状可以在通过应力施加层纵向压缩应力时提供通道区域内的增强的垂直拉伸应力。

6. 发明授权

US07528050B2 High performance field effect transistors on SOI substrate with stress-inducing material as buried insulator and methods 失效
标题翻译：具有应力诱导材料的SOI衬底上的高性能场效应晶体管作为掩埋绝缘体和方法
公开(公告)号：US07528050B2
公开(公告)日：2009-05-05
申请号：US12115106
申请日：2008-05-05
申请人： Judson R. Holt , Qiqing C. Ouyang
发明人： Judson R. Holt , Qiqing C. Ouyang
IPC分类号： H01L21/46
CPC分类号： H01L29/78 , H01L21/76254 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
摘要翻译：本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

7. 发明申请

US20080206951A1 HIGH PERFORMANCE FIELD EFFECT TRANSISTORS ON SOI SUBSTRATE WITH STRESS-INDUCING MATERIAL AS BURIED INSULATOR AND METHODS 失效
标题翻译：具有应力诱导材料的SOI衬底上的高性能场效应晶体管作为绝缘绝缘体和方法
公开(公告)号：US20080206951A1
公开(公告)日：2008-08-28
申请号：US12115106
申请日：2008-05-05
申请人： Judson R. Holt , Qiqing C. Ouyang
发明人： Judson R. Holt , Qiqing C. Ouyang
IPC分类号： H01L21/86
CPC分类号： H01L29/78 , H01L21/76254 , H01L27/1203 , H01L27/1207 , H01L29/7846
摘要： The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.
摘要翻译：本发明提供了一种半导体结构，其包括绝缘体（SOI）上的高性能场效应晶体管（FET），其绝缘体是预选几何形状的应力诱导材料。这种结构可以实现单轴应力的性能提高，并且通道中的应力不依赖于局部触点的布局设计。广义而言，本发明涉及一种包括上半导体层和底半导体层的半导体结构，其中所述上半导体层通过具有预选的应力诱导绝缘体在至少一个区域中与所述底部半导体层分离几何形状，所述应力诱导绝缘子在上半导体层上施加应变。

8. 发明授权

US07002214B1 Ultra-thin body super-steep retrograde well (SSRW) FET devices 有权
标题翻译：超薄体超陡逆行井（SSRW）FET器件
公开(公告)号：US07002214B1
公开(公告)日：2006-02-21
申请号：US10710736
申请日：2004-07-30
申请人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
发明人： Diane C. Boyd , Judson R. Holt , MeiKei Ieong , Renee T. Mo , Zhibin Ren , Ghavam G. Shahidi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/823892 , H01L21/84 , H01L29/66772 , H01L29/78609 , H01L29/78618 , H01L29/78696
摘要： A method of manufacture of a Super Steep Retrograde Well Field Effect Transistor device starts with an SOI layer formed on a substrate, e.g. a buried oxide layer. Thin the SOI layer to form an ultra-thin SOI layer. Form an isolation trench separating the SOI layer into N and P ground plane regions. Dope the N and P ground plane regions formed from the SOI layer with high levels of N-type and P-type dopant. Form semiconductor channel regions above the N and P ground plane regions. Form FET source and drain regions and gate electrode stacks above the channel regions. Optionally form a diffusion retarding layer between the SOI ground plane regions and the channel regions.
摘要翻译：超陡逆行井场效应晶体管器件的制造方法从形成在衬底上的SOI层开始。掩埋氧化层。使SOI层变薄以形成超薄SOI层。形成将SOI层分离成N和P接地平面区域的隔离沟槽。用高水平的N型和P型掺杂剂掺杂由SOI层形成的N和P接地平面区域。在N和P接地平面区域之上形成半导体沟道区。在沟道区域上方形成FET源极和漏极区域以及栅极电极堆叠。可选地，在SOI接地平面区域和沟道区域之间形成扩散延迟层。

9. 发明授权

US09059316B2 Structure and method for mobility enhanced MOSFETs with unalloyed silicide 有权
标题翻译：具有非合金化硅化物的迁移率增强型MOSFET的结构和方法
公开(公告)号：US09059316B2
公开(公告)日：2015-06-16
申请号：US13397860
申请日：2012-02-16
申请人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
发明人： Yaocheng Liu , Dureseti Chidambarrao , Oleg Gluschenkov , Judson R. Holt , Renee T. Mo , Kern Rim
IPC分类号： H01L21/8238 , H01L21/768 , H01L21/84 , H01L27/12 , H01L29/66 , H01L29/78 , H01L27/32 , H01L29/165
CPC分类号： H01L21/823864 , H01L21/76886 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L27/3279 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.
摘要翻译：虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

10. 发明申请

US20080128712A1 RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 有权
标题翻译：用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术
公开(公告)号：US20080128712A1
公开(公告)日：2008-06-05
申请号：US12028191
申请日：2008-02-08
申请人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
发明人： Ashima B. Chakravarti , Dureseti Chidambarrao , Judson R. Holt , Yaocheng Liu , Kern Rim
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译：通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C）用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积具有足够高的替代碳含量的Si：C固有地是非选择性的。

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