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1. 发明授权

US07064064B2 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US07064064B2
公开(公告)日：2006-06-20
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/44
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

2. 发明授权

US06975032B2 Copper recess process with application to selective capping and electroless plating 有权
公开(公告)号：US06975032B2
公开(公告)日：2005-12-13
申请号：US10319967
申请日：2002-12-16
申请人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy J. Dalton , Kenneth M. Davis , Chao-Kun Hu , Fen F. Jamin , Steffen K. Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael F. Lofaro , Sandra G. Malhotra , Chandrasekhar Narayan , David L. Rath , Judith M. Rubino , Katherine L. Saenger , Andrew H. Simon , Sean P. E. Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

3. 发明申请

US20050158985A1 Copper recess process with application to selective capping and electroless plating 有权
标题翻译：铜凹槽工艺，适用于选择性封盖和无电镀
公开(公告)号：US20050158985A1
公开(公告)日：2005-07-21
申请号：US11058783
申请日：2005-02-16
申请人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
发明人： Shyng-Tsong Chen , Timothy Dalton , Kenneth Davis , Chao-Kun Hu , Fen Jamin , Steffen Kaldor , Mahadevaiyer Krishnan , Kaushik Kumar , Michael Lofaro , Sandra Malhotra , Chandrasekhar Narayan , David Rath , Judith Rubino , Katherine Saenger , Andrew Simon , Sean Smith , Wei-tsu Tseng
IPC分类号： H01L21/768 , H01L23/532 , H01L21/44 , H01L21/4763 , H01L21/48
CPC分类号： H01L21/76849 , H01L21/76834 , H01L21/76847 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.
摘要翻译：公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

4. 发明授权

US07468320B2 Reduced electromigration and stressed induced migration of copper wires by surface coating 有权
标题翻译：通过表面涂层减少电迁移和应力诱导的铜线迁移
公开(公告)号：US07468320B2
公开(公告)日：2008-12-23
申请号：US11183773
申请日：2005-07-19
申请人： Chao-Kun Hu , Robert Rosenberg , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
发明人： Chao-Kun Hu , Robert Rosenberg , Judith M. Rubino , Carlos J. Sambucetti , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/288 , H01L21/76849 , H01L21/76864 , H01L23/53228 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.
摘要翻译：本发明的想法是在沉积层间电介质之前，通过1-20nm厚的金属层将芯片上互连（BEOL）布线中的图案化Cu导线的自由表面涂覆。该涂层足够薄，以便消除对通过抛光进行附加平面化的需要，同时提供了防止氧化和表面或Cu的扩散的保护，这已经被本发明人鉴定为导致金属线路故障的主要贡献者通过电迁移和热压力消除。此外，金属层增加了Cu和电介质之间的粘合强度，从而进一步增加寿命并且有助于工艺产量。自由表面是在镶嵌工艺中的CMP（化学机械抛光）或通过图形化Cu布线的干蚀刻工艺的直接结果。提出通过选择性方法将金属覆盖层沉积到Cu上以最小化进一步的加工。尽管可以使用金属或金属形成化合物的化学气相沉积（CVD），但我们已经使用了无电金属涂层，例如CoWP，CoSnP和Pd来说明显着的可靠性优点。

5. 发明授权

US09059176B2 Copper interconnect with CVD liner and metallic cap 有权
标题翻译：铜连接与CVD衬垫和金属帽
公开(公告)号：US09059176B2
公开(公告)日：2015-06-16
申请号：US13451947
申请日：2012-04-20
申请人： Frieder Hainrich Baumann , Chao-Kun Hu , Andrew H. Simon , Tibor Bolom , Koichi Motoyama , Chengyu Charles Niu
发明人： Frieder Hainrich Baumann , Chao-Kun Hu , Andrew H. Simon , Tibor Bolom , Koichi Motoyama , Chengyu Charles Niu
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76804 , H01L21/76843 , H01L21/76849 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
摘要翻译：具有位于邻近侧壁的扩散阻挡层的结构和在介电材料层中蚀刻的开口的底部。该结构还具有直接位于扩散阻挡层顶部的金属衬垫，直接位于金属衬垫顶部上的种子层，其中种子层由包括铜的材料制成，铜材料直接位于种子顶部层，直接位于铜材料的顶部和选择性上的金属盖，以及直接位于金属盖的顶部并且邻近金属盖的封盖层。

6. 发明申请

US20130277842A1 COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP 有权
公开(公告)号：US20130277842A1
公开(公告)日：2013-10-24
申请号：US13451947
申请日：2012-04-20
申请人： Frieder Hainrich Baumann , Chao-Kun Hu , Andrew H. Simon , Tibor Bolom , Koichi Motoyama , Chengyu Charles Niu
发明人： Frieder Hainrich Baumann , Chao-Kun Hu , Andrew H. Simon , Tibor Bolom , Koichi Motoyama , Chengyu Charles Niu
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/76804 , H01L21/76843 , H01L21/76849 , H01L21/76873 , H01L2924/0002 , H01L2924/00
摘要： A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.

7. 发明授权

US08232646B2 Interconnect structure for integrated circuits having enhanced electromigration resistance 有权
标题翻译：具有增强的电迁移电阻的集成电路的互连结构
公开(公告)号：US08232646B2
公开(公告)日：2012-07-31
申请号：US12691213
申请日：2010-01-21
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76846 , H01L21/76847 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line.
摘要翻译：用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分。

8. 发明授权

US06399496B1 Copper interconnection structure incorporating a metal seed layer 有权
标题翻译：包含金属种子层的铜互连结构
公开(公告)号：US06399496B1
公开(公告)日：2002-06-04
申请号：US09714504
申请日：2000-11-16
申请人： Daniel Charles Edelstein , James McKell Edwin Harper , Chao-Kun Hu , Andrew H. Simon , Cyprian Emeka Uzoh
发明人： Daniel Charles Edelstein , James McKell Edwin Harper , Chao-Kun Hu , Andrew H. Simon , Cyprian Emeka Uzoh
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.
摘要翻译：本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

9. 发明申请

US20110175226A1 INTERCONNECT STRUCTURE FOR INTEGRATED CIRCUITS HAVING ENHANCED ELECTROMIGRATION RESISTANCE 有权
标题翻译：具有增强电阻率的集成电路的互连结构
公开(公告)号：US20110175226A1
公开(公告)日：2011-07-21
申请号：US12691213
申请日：2010-01-21
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Stephan Grunow , Chao-Kun Hu , Naftali E. Lustig , Andrew H. Simon , Ping-Chuan Wang
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76805 , H01L21/76816 , H01L21/76846 , H01L21/76847 , H01L23/522 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit (IC) device includes a metal line formed within a dielectric layer, the metal line having one or more vertical diffusion barriers therein; wherein the one or more vertical diffusion barriers correspond to a liner material of a via formed above the metal line, with the via extending completely through a thickness of the metal line such that a bottom most portion of the via comprises a portion of the metal line
摘要翻译：用于集成电路（IC）器件的互连结构包括形成在电介质层内的金属线，所述金属线在其中具有一个或多个垂直扩散阻挡层; 其中所述一个或多个垂直扩散屏障对应于在所述金属线上方形成的通孔的衬垫材料，所述通孔完全延伸穿过所述金属线的厚度，使得所述通孔的最底部包括所述金属线的一部分

10. 发明授权

US07737528B2 Structure and method of forming electrically blown metal fuses for integrated circuits 有权
标题翻译：为集成电路形成电熔金属保险丝的结构和方法
公开(公告)号：US07737528B2
公开(公告)日：2010-06-15
申请号：US12132337
申请日：2008-06-03
申请人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
发明人： Griselda Bonilla , Kaushik Chanda , Ronald G. Filippi , Jeffrey P. Gambino , Stephan Grunow , Chao-Kun Hu , Sujatha Sankaran , Andrew H. Simon , Theodorus E. Standaert
IPC分类号： H01L21/768
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure for an integrated circuit device includes an elongated metal interconnect layer defined within an insulating layer; a metal cap layer formed on only a portion of a top surface of the metal interconnect layer; and a dielectric cap layer formed on both the metal cap layer and the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon; wherein the remaining portions of the metal interconnect layer not having the metal cap layer formed thereon are susceptible to an electromigration failure mechanism so as to facilitate programming of the fuse structure by application of electric current through the elongated metal interconnect layer.
摘要翻译：用于集成电路器件的熔丝结构包括限定在绝缘层内的细长金属互连层; 仅在所述金属互连层的顶表面的一部分上形成的金属盖层; 以及形成在所述金属盖层和所述金属互连层的其余部分上的电介质盖层，其不形成有所述金属盖层; 其中不具有形成在其上的金属覆盖层的金属互连层的其余部分容易受到电迁移故障机制的影响，以便通过施加通过细长金属互连层的电流来编程熔丝结构。

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