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1. 发明授权

US07276787B2 Silicon chip carrier with conductive through-vias and method for fabricating same 有权
标题翻译：具有导电通孔的硅芯片载体及其制造方法
公开(公告)号：US07276787B2
公开(公告)日：2007-10-02
申请号：US10729254
申请日：2003-12-05
申请人： Daniel Charles Edelstein , Paul Stephen Andry , Leena Paivikki Buchwalter , Jon Alfred Casey , Sherif A. Goma , Raymond R. Horton , Gareth Geoffrey Hougham , Michael Wayne Lane , Xiao Hu Liu , Chirag Suryakant Patel , Edmund Juris Sprogis , Michelle Leigh Steen , Brian Richard Sundlof , Cornelia K. Tsang , George Frederick Walker
发明人： Daniel Charles Edelstein , Paul Stephen Andry , Leena Paivikki Buchwalter , Jon Alfred Casey , Sherif A. Goma , Raymond R. Horton , Gareth Geoffrey Hougham , Michael Wayne Lane , Xiao Hu Liu , Chirag Suryakant Patel , Edmund Juris Sprogis , Michelle Leigh Steen , Brian Richard Sundlof , Cornelia K. Tsang , George Frederick Walker
IPC分类号： H01L23/48 , H01L23/498 , H01L21/4763 , H01L29/40 , H01L23/52
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译：一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于或者与衬底的密切匹配。导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯，具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

2. 发明授权

US06646345B2 Method for forming Co-W-P-Au films 有权
公开(公告)号：US06646345B2
公开(公告)日：2003-11-11
申请号：US09966629
申请日：2001-09-27
申请人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
发明人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , C23C18/1651 , C23C18/1841 , C23C18/44 , C23C18/50 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76864 , H01L21/76874 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.

3. 发明授权

US06399496B1 Copper interconnection structure incorporating a metal seed layer 有权
标题翻译：包含金属种子层的铜互连结构
公开(公告)号：US06399496B1
公开(公告)日：2002-06-04
申请号：US09714504
申请日：2000-11-16
申请人： Daniel Charles Edelstein , James McKell Edwin Harper , Chao-Kun Hu , Andrew H. Simon , Cyprian Emeka Uzoh
发明人： Daniel Charles Edelstein , James McKell Edwin Harper , Chao-Kun Hu , Andrew H. Simon , Cyprian Emeka Uzoh
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76871 , H01L21/76877 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses an interconnection structure for providing electrical communication with an electronic device which includes a body that is formed substantially of copper and a seed layer of either a copper alloy or a metal that does not contain copper sandwiched between the copper conductor body and the electronic device for improving the electromigration resistance, the adhesion property and other surface properties of the interconnection structure. The present invention also discloses methods for forming an interconnection structure for providing electrical connections to an electronic device by first depositing a seed layer of copper alloy or other metal that does not contain copper on an electronic device, and then forming a copper conductor body on the seed layer intimately bonding to the layer such that electromigration resistance, adhesion and other surface properties of the interconnection structure are improved.
摘要翻译：本发明公开了一种用于与电子设备进行电连接的互连结构，该电子设备包括基本上由铜形成的主体和不包含铜的铜合金或金属的籽晶层夹在铜导体本体和用于提高互连结构的电迁移电阻，粘附性等表面性质的电子器件。本发明还公开了用于形成互连结构的方法，该互连结构用于通过首先在电子器件上沉积铜合金或不含铜的其它金属的种子层，然后在其上形成铜导体，从而提供与电子器件的电连接种子层紧密地结合到层上，使得互连结构的电迁移阻力，粘附性和其它表面性质得到改善。

4. 发明授权

US06291885B1 Thin metal barrier for electrical interconnections 失效
标题翻译：用于电互连的薄金属屏障
公开(公告)号：US06291885B1
公开(公告)日：2001-09-18
申请号：US08896925
申请日：1997-07-18
申请人： Cyril Cabral, Jr. , Patrick William DeHaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
发明人： Cyril Cabral, Jr. , Patrick William DeHaven , Daniel Charles Edelstein , David Peter Klaus , James Manley Pollard, III , Carol L. Stanis , Cyprian Emeka Uzoh
IPC分类号： H01L2348
CPC分类号： H01L21/76846 , H01L21/76843 , H01L23/53223 , H01L23/53233 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L24/11 , H01L24/12 , H01L29/4933 , H01L2224/05124 , H01L2224/05181 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10329 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/3025 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.
摘要翻译：描述了用于电互连的互连结构和阻挡层，其结合了诸如Cu的第一材料和诸如Al，W和PbSn的第二材料之间的六方相中的TaN层。六方相中的TaN多层和α相中的Ta也被描述为阻挡层。本发明克服了在500℃的温度退火期间将Cu扩散到期望分离的材料中的问题。

5. 发明授权

US6114937A Integrated circuit spiral inductor 失效
标题翻译：集成电路螺旋电感
公开(公告)号：US6114937A
公开(公告)日：2000-09-05
申请号：US949316
申请日：1997-10-14
申请人： Joachim Norbert Burghartz , Daniel Charles Edelstein , Christopher Vincent Jahnes , Cyprian Emeka Uzoh
发明人： Joachim Norbert Burghartz , Daniel Charles Edelstein , Christopher Vincent Jahnes , Cyprian Emeka Uzoh
IPC分类号： H01F17/00 , H01F17/06 , H01F27/28 , H01F30/16 , H01F41/04 , H01L23/522 , H01F5/00
CPC分类号： H01L23/5227 , H01F17/0006 , H01F17/0033 , H01F27/2804 , H01F27/2895 , H01F30/16 , H01F41/042 , H01F41/046 , H01F17/06 , H01L2924/0002 , Y10T29/4902
摘要： High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.
摘要翻译：公开了与硅非常大规模集成（VLSI）处理兼容的高质量因子（Q）螺旋和环形电感器和变压器，消耗小的IC区域并在高频下操作。螺旋电感器具有沉积在形成在衬底上的电介质层中的沟槽中的螺旋金属线圈。金属线圈封装在铁磁衬垫和盖层中，并通过电介质层中的金属填充通孔连接到地下通道接触。螺旋电感器还包括由金属螺旋线圈包围的铁磁芯线。通过垂直堆叠两个螺旋电感器或将它们并排放置在形成在金属线圈和芯线下方的铁磁桥上，形成螺旋形变压器。环形电感器包括具有铁磁条的芯的环形金属线圈。环形金属线圈被分成两个线圈，每个线圈具有一对端口以形成环形变压器。

6. 发明授权

US6063651A Method for activating fusible links on a circuit substrate 失效
标题翻译：用于激活电路基板上的可熔链节的方法
公开(公告)号：US6063651A
公开(公告)日：2000-05-16
申请号：US18145
申请日：1998-02-03
申请人： Daniel Charles Edelstein , Chandrasekhar Narayan
发明人： Daniel Charles Edelstein , Chandrasekhar Narayan
IPC分类号： H01L23/525 , H01L21/82
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size laser beam having a lower wavelength to be employed for interrupting the fusible links. The substrate is cooled by a refrigeration coil in heat transfer with the fixture holding the substrate. Moisture formation is avoided by placing the substrate and laser source in a controlled atmosphere.
摘要翻译：一种用于激活电路基板上的可熔链节的方法和装置。电路基板被支撑在被冷却到低于环境温度的固定装置中。电路基板的冷却减少了基板的能量吸收，允许采用较低波长的较小的点尺寸的激光束来中断熔丝。基板通过热传递的冷冻盘管冷却，夹具固定基板。通过将基板和激光源放置在受控的气氛中来避免水分形成。

7. 发明申请

US20100252775A1 METHOD FOR FORMING AN INDIUM CAP LAYER 失效
标题翻译：形成印刷层的方法
公开(公告)号：US20100252775A1
公开(公告)日：2010-10-07
申请号：US12819697
申请日：2010-06-21
申请人： Maurice McGlashan-Powell , Eugene J. O'Sullivan , Daniel Charles Edelstein
发明人： Maurice McGlashan-Powell , Eugene J. O'Sullivan , Daniel Charles Edelstein
IPC分类号： C09K13/06 , C09K13/00
CPC分类号： C09K13/04
摘要： An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.
摘要翻译：通过在由层间电介质分离的金属互连件的表面上覆盖沉积铟，然后选择性地化学蚀刻位于层间电介质上的铟而形成铟盖层，留下铟盖层。提供含有强酸的蚀刻剂用于选择性地除去铟。

8. 发明授权

US06709562B1 Method of making electroplated interconnection structures on integrated circuit chips 有权
标题翻译：在集成电路芯片上制作电镀互连结构的方法
公开(公告)号：US06709562B1
公开(公告)日：2004-03-23
申请号：US09348632
申请日：1999-07-06
申请人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Hariklia Deligianni , John Owen Dukovic , Daniel Charles Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth Parker Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： C25D712
CPC分类号： H01L21/2885 , C25D3/38 , C25D7/123 , H01L21/76877
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译：描述了用于制造用于集成电路芯片的亚微米互连结构的过程。通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。这种方法在不留下空隙或接缝的情况下超滤特征的能力是独一无二的，优于其他沉积方法。以这种方式使用电镀Cu的结构的电迁移电阻优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。

9. 发明授权

US06525427B2 BEOL decoupling capacitor 有权
公开(公告)号：US06525427B2
公开(公告)日：2003-02-25
申请号：US10055704
申请日：2002-01-22
申请人： Peter Richard Duncombe , Daniel Charles Edelstein , Robert Benjamin Laibowitz , Deborah Ann Neumayer , Tak Hung Ning , Robert Rosenberg , Thomas Mcarraoll Shaw
发明人： Peter Richard Duncombe , Daniel Charles Edelstein , Robert Benjamin Laibowitz , Deborah Ann Neumayer , Tak Hung Ning , Robert Rosenberg , Thomas Mcarraoll Shaw
IPC分类号： H01L2348
CPC分类号： H01L28/55 , H01L21/31691 , H01L23/5223 , H01L23/5329 , H01L23/642 , H01L2924/0002 , H01L2924/00
摘要： An amorphous dielectric material having a dielectric constant of 10 or greater is provided herein for use in fabricating capacitors in integrated circuit applications. The amorphous dielectric material is formed using temperatures below 450° C.; therefore the BEOL metallurgy is not adversely affected. The amorphous dielectric material of the present invention exhibits good conformality and a low leakage current. Damascene devices containing the capacitor of the present invention are also disclosed.

10. 发明授权

US06323128B1 Method for forming Co-W-P-Au films 失效
标题翻译： Co-W-P-Au薄膜的制备方法
公开(公告)号：US06323128B1
公开(公告)日：2001-11-27
申请号：US09320499
申请日：1999-05-26
申请人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
发明人： Carlos Juan Sambucetti , Judith Marie Rubino , Daniel Charles Edelstein , Cyryl Cabral, Jr. , George Frederick Walker , John G Gaudiello , Horatio Seymour Wildman
IPC分类号： H01L21441
CPC分类号： H01L21/76846 , C23C18/1651 , C23C18/1841 , C23C18/44 , C23C18/50 , H01L21/288 , H01L21/76849 , H01L21/76858 , H01L21/76864 , H01L21/76874 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions. After the pre-treated substrate is rinsed in a first rinsing step by distilled water, the substrate is electroless plated a Co—W—P film on the surfaces of the copper conductive regions in a first plating solution that contains cobalt ions, tungstate ions, citrate ions and a reducing agent. After the substrate coated with the Co—W—P film is rinsed in a second rinsing step by distilled water, the substrate is immersed in a second electroless plating solution for depositing a Au layer on top of the Co—W—P film. The present invention novel quaternary alloy film can be used as an effective diffusion barrier layer between a copper interconnect and silicon substrate or SiO2 dielectric layers.
摘要翻译：公开了一种用于在半导体结构中的铜互连上用作扩散阻挡层的Co-W-P-Au的四元合金膜的形成方法和包含这种膜的器件。在该方法中，首先通过两个单独的预处理步骤对具有铜导电区域的基板进行预处理。在第一步骤中，将衬底浸入H 2 SO 4冲洗溶液中，接着在含有钯离子的溶液中浸渍一段足以使离子沉积在铜导电区域表面上的时间。然后将基底浸入含有至少15g / l柠檬酸钠或EDTA的溶液中，以从铜导电区域的表面除去过量的钯离子。在通过蒸馏水在第一冲洗步骤中冲洗预处理的基材之后，在包含钴离子，钨酸根离子，柠檬酸根离子的第一电镀液中，在铜导电区域的表面上化学镀Co-WP膜和还原剂。在用Co-W-P膜涂布的基材在第二次漂洗步骤中用蒸馏水冲洗后，将基板浸渍在Co-W-P膜顶部沉积Au层的第二无电镀液中。本发明的新型四元合金膜可以用作铜互连和硅衬底或SiO 2电介质层之间的有效扩散阻挡层。

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