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1. 发明授权

US5661068A Method of fabricating a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US5661068A
公开(公告)日：1997-08-26
申请号：US467290
申请日：1995-06-06
申请人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
发明人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/265
CPC分类号： H01L28/84 , H01L21/3213 , H01L21/32131 , H01L21/76838 , Y10S148/014 , Y10S438/964
摘要： A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.
摘要翻译：本发明的制造半导体器件的方法包括以下步骤：在硅上形成具有不均匀厚度的氧化膜; 使用含有金属元素的气体还原至少一部分氧化物膜，并且通过使硅的暴露表面与气体反应，在硅上生长含有金属元素的金属膜; 并除去金属膜。

2. 发明授权

US5474949A Method of fabricating capacitor or contact for semiconductor device by forming uneven oxide film and reacting silicon with metal containing gas 失效
标题翻译：通过形成不均匀的氧化膜并使硅与含金属的气体反应来制造用于半导体器件的电容器或接触器的方法
公开(公告)号：US5474949A
公开(公告)日：1995-12-12
申请号：US9583
申请日：1993-01-26
申请人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
发明人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/473
CPC分类号： H01L28/84 , H01L21/3213 , H01L21/32131 , H01L21/76838 , Y10S148/014 , Y10S438/964
摘要： A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.
摘要翻译：本发明的制造半导体器件的方法包括以下步骤：在硅上形成具有不均匀厚度的氧化膜; 使用含有金属元素的气体还原至少一部分氧化物膜，并且通过使硅的暴露表面与气体反应，在硅上生长含有金属元素的金属膜; 并除去金属膜。

3. 发明授权

US5693557A Method of fabricating a semiconductor device 失效
公开(公告)号：US5693557A
公开(公告)日：1997-12-02
申请号：US590086
申请日：1996-01-24
申请人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
发明人： Shuji Hirao , Hisashi Ogawa , Yuka Terai , Mitsuru Sekiguchi , Masanori Fukumoto , Isao Miyanaga
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/768 , H01L21/70
CPC分类号： H01L28/84 , H01L21/3213 , H01L21/32131 , H01L21/76838 , Y10S148/014 , Y10S438/964
摘要： A method of the invention for fabricating a semiconductor device includes the steps of: forming an oxide film having a non-uniform thickness on silicon; reducing at least a portion of the oxide film using gas containing a metal element, and growing a metal film containing the metal element on the silicon by reacting an exposed surface of the silicon with the gas; and removing the metal film.

4. 发明授权

US5714400A Method for forming a memory device by utilizing variations in resistance value 失效
标题翻译：通过利用电阻值的变化形成存储器件的方法
公开(公告)号：US5714400A
公开(公告)日：1998-02-03
申请号：US668179
申请日：1996-06-21
申请人： Shuji Hirao , Hideko Okada , Kousaku Yano
发明人： Shuji Hirao , Hideko Okada , Kousaku Yano
IPC分类号： H01L27/10 , G11C17/10 , H01L21/822 , H01L21/8246 , H01L27/105 , H01L21/8242
CPC分类号： G11C13/00 , G11C13/0069 , G11C17/10 , H01L21/822 , H01L27/101 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/14 , H01L45/1616 , H01L45/1683 , G11C2013/0073 , G11C2213/33 , G11C2213/56 , G11C2213/77
摘要： On an insulating substrate are formed first aluminum interconnections. In openings formed in a silicon dioxide film are formed unit cells each consisting of a tungsten electrode and an aluminum alloy electrode containing silicon. Over the silicon dioxide film are formed a large number of linear second aluminum interconnections which are orthogonal to the first aluminum interconnections. At the individual intersections of the first and second aluminum interconnections are disposed the unit cells so as to compose a memory cell array. When a large current is allowed to flow through the unit cell, silicon in the aluminum alloy electrode moves in a direction opposite to the current flow and is precipitated in the aluminum electrode in the vicinity of the interface with the tungsten electrode, resulting in an increase in resistance value. When a large current is allowed to flow through the unit cell in the opposite direction, silicon is diffused, resulting in a reduction in resistance value. Data can be read by measuring the magnitude of the resistance value with an extremely small current and judging whether it is in a high state or in a low state.
摘要翻译：在绝缘基板上形成第一铝互连。在二氧化硅膜形成的开口中形成有由钨电极和含有硅的铝合金电极组成的单电池。在二氧化硅膜上形成大量与第一铝互连正交的线性第二铝互连。在第一和第二铝互连的各个交叉处设置单元电池以构成存储单元阵列。当允许大电流流过单元电池时，铝合金电极中的硅沿着与电流相反的方向移动，并且在与钨电极的界面附近的铝电极中沉淀，导致增加电阻值。当允许大电流以相反方向流过单位电池时，硅扩散，导致电阻值的降低。可以通过以极小的电流测量电阻值的大小并判断其是处于高状态还是处于低状态来读取数据。

5. 发明授权

US07001841B2 Production method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07001841B2
公开(公告)日：2006-02-21
申请号：US10643980
申请日：2003-08-20
申请人： Shuji Hirao , Takeshi Harada , Kazushi Nii , Takenobu Kishida , Atsushi Ikeda , Kazunori Tsuji
发明人： Shuji Hirao , Takeshi Harada , Kazushi Nii , Takenobu Kishida , Atsushi Ikeda , Kazunori Tsuji
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L21/76874 , H01L21/76877
摘要： After a thin first conductive film is formed on a barrier film having a crystal structure, a second conductive film is formed on the first conductive film. Thereafter, the first conductive film and the second conductive film are heated such that the first and second conductive films are integrated to form a third conductive film.
摘要翻译：在具有晶体结构的阻挡膜上形成薄的第一导电膜之后，在第一导电膜上形成第二导电膜。此后，第一导电膜和第二导电膜被加热，使得第一和第二导电膜被一体化以形成第三导电膜。

6. 发明申请

US20070134929A1 Etching method and etching apparatus 审中-公开
标题翻译：蚀刻方法和蚀刻装置
公开(公告)号：US20070134929A1
公开(公告)日：2007-06-14
申请号：US11580945
申请日：2006-10-16
申请人： Shuji Hirao
发明人： Shuji Hirao
IPC分类号： H01L21/465 , C23F1/00
CPC分类号： H01L21/02087 , C23F1/00 , C23F1/08 , H01L21/6708
摘要： While a semiconductor substrate having a metal film formed thereover by electrolytic plating is rotated, an etching solution for the metal film is supplied to the peripheral portion of the metal film at a first flow rate and then the etching solution is continuously supplied at a second flow rate, which is lower than the first flow rate.
摘要翻译：当通过电解电镀在其上形成金属膜的半导体衬底旋转时，以第一流量将金属膜的蚀刻溶液供应到金属膜的周边部分，然后以第二流动连续地供给蚀刻溶液比率低于第一流量。

7. 发明授权

US5385867A Method for forming a multi-layer metallic wiring structure 失效
标题翻译：用于形成多层金属布线结构的方法
公开(公告)号：US5385867A
公开(公告)日：1995-01-31
申请号：US216968
申请日：1994-03-24
申请人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
发明人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/283 , H01L21/31
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , Y10S438/948
摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.
摘要翻译：在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处第一层金属布线。在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

8. 发明申请

US20100244265A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100244265A1
公开(公告)日：2010-09-30
申请号：US12813699
申请日：2010-06-11
申请人： Shuji Hirao
发明人： Shuji Hirao
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/288 , H01L21/76832 , H01L21/76834 , H01L21/76849 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Wiring grooves are formed on a first interlayer insulating film 2 on a semiconductor substrate 1; first Cu wires 5 are formed by stacking first Cu films 4 in the wiring grooves; a first liner film 6 is formed on the first Cu wires 5 and the first interlayer insulating film 2; openings 13 are partially formed on the first Cu wires 5 so as to expose the surfaces of the first Cu wires 5 on the first liner film 6; and cap metal films 7 are formed on the surfaces of the first Cu wires 5 exposed in the openings 13.
摘要翻译：在半导体衬底1上的第一层间绝缘膜2上形成接线槽; 第一Cu线5通过在布线槽中堆叠第一Cu膜4而形成; 在第一Cu线5和第一层间绝缘膜2上形成第一衬里膜6; 开口13部分地形成在第一Cu线5上，以露出第一衬里膜6上的第一Cu线5的表面; 并且在露出在开口13中的第一Cu线5的表面上形成帽金属膜7。

9. 发明授权

US07217353B2 Method and apparatus for plating substrate 有权
标题翻译：电镀基板的方法和装置
公开(公告)号：US07217353B2
公开(公告)日：2007-05-15
申请号：US10624564
申请日：2003-07-23
申请人： Shuji Hirao
发明人： Shuji Hirao
IPC分类号： C25D5/00 , C25D5/02 , C25D5/34 , C23C28/02
CPC分类号： H01L21/2885 , C25D7/123 , C25D21/00 , C25D21/04
摘要： After bubbles adsorbed to a substrate are removed by rotating the substrate in a plating solution at a higher speed or after the wettability of the surface of the substrate to be plated is improved before the substrate is immersed in the plating solution, the substrate is rotated in the plating solution at a lower speed so that a plating process is performed with respect to the substrate.
摘要翻译：吸附到基板上的气泡通过以较高的速度旋转镀液中的基板或者在将基板浸渍在电镀液中之前改善被镀基板的表面的润湿性而被去除之后，将基板旋转电镀液以较低的速度进行，从而对基板进行电镀处理。

10. 发明授权

US5753536A Semiconductor device and associated fabrication method 失效
标题翻译：半导体器件及相关制造方法
公开(公告)号：US5753536A
公开(公告)日：1998-05-19
申请号：US520252
申请日：1995-08-28
申请人： Tatsuo Sugiyama , Shuji Hirao , Kousaku Yano , Noboru Nomura
发明人： Tatsuo Sugiyama , Shuji Hirao , Kousaku Yano , Noboru Nomura
IPC分类号： H01L21/98 , H01L25/065 , H01L21/60
CPC分类号： H01L23/544 , H01L21/76898 , H01L24/05 , H01L24/12 , H01L24/16 , H01L24/80 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2224/0401 , H01L2224/05571 , H01L2224/08145 , H01L2224/13099 , H01L2224/80141 , H01L2224/80357 , H01L2224/80895 , H01L2224/80896 , H01L2224/81121 , H01L2224/81801 , H01L2224/81894 , H01L2224/83894 , H01L2224/9202 , H01L2225/06513 , H01L2225/06593 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3511
摘要： A first electrode and a first insulating layer of electrode insulation are formed on a first semiconductor substrate. A second electrode and a second insulating layer of electrode insulation are formed on a second semiconductor substrate. The first semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement. Likewise, the second semiconductor substrate has at its surface a pattern of recesses/projections (i.e., a pattern of sawteeth in cross section) at regular intervals in stripe arrangement, wherein the pattern of the second semiconductor substrate has a phase shift of 180 degrees with respect to the pattern of the first semiconductor substrate. The first and second semiconductor substrates are bonded together with their patterns in engagement.
摘要翻译：在第一半导体衬底上形成有电极绝缘体的第一电极和第一绝缘层。在第二半导体衬底上形成第二电极和电极绝缘的第二绝缘层。第一半导体衬底在其表面上以条纹布置的规则间隔在其表面处具有凹槽/突起的图案（即横截面的锯齿形图案）。类似地，第二半导体衬底在其表面上在条纹布置中以规则的间隔在其表面处具有凹槽/突起的图案（即，横截面的锯齿形图案），其中第二半导体衬底的图案具有180度的相移，相对于第一半导体衬底的图案。第一和第二半导体衬底以它们的图案接合在一起。

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