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1. 发明授权

US5385867A Method for forming a multi-layer metallic wiring structure 失效
标题翻译：用于形成多层金属布线结构的方法
公开(公告)号：US5385867A
公开(公告)日：1995-01-31
申请号：US216968
申请日：1994-03-24
申请人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
发明人： Tetsuya Ueda , Kousaku Yano , Tomoyasu Murakami , Michinari Yamanaka , Shuji Hirao , Noboru Nomura
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/522 , H01L21/283 , H01L21/31
CPC分类号： H01L21/76847 , H01L21/76844 , H01L21/76877 , H01L21/76885 , H01L23/5226 , H01L2924/0002 , Y10S438/948
摘要： After accumulating a BPSG film layer on a silicon substrate, a first Al--Si--Cu film layer, a W film layer and a second Al--Si--Cu film layer are successively accumulated on this BPSG film layer. A resist pattern with wide-width and narrow-width pattern portions is formed on the second Al--Si--Cu film layer. The wide-width pattern portion is provided at a position corresponding to a contact for connecting a first-layer metallic wiring and a second-layer metallic wiring, while the narrow-width pattern portion is provided at a position corresponding to a wiring portion for the first-layer metallic wiring. After applying first etching on the second Al--Si--Cu film layer with a mask of the resist patter, second etching is applied on the W film layer. Thereafter, by applying third etching, the resist pattern remaining on the first-layer metallic wiring is removed and the first Al--Si--Cu film layer is transfigured into a tall metallic film portion and a short metallic film portion. After accumulating an inter-layer insulating film layer on the first Al--Si--Cu film layer, etchback is applied on this inter-layer insulating film layer until the top of the tall metallic film portion is bared. Then, the second-layer metallic wiring is formed on the inter-layer insulating film layer so that the second-layer metallic wiring is connected with the tall metallic film portion.
摘要翻译：在硅衬底上积累BPSG膜层之后，第一Al-Si-Cu膜层，W膜层和第二Al-Si-Cu膜层依次堆积在该BPSG膜层上。在第二Al-Si-Cu膜层上形成具有宽幅和窄宽图案部分的抗蚀剂图案。宽幅图形部分设置在与用于连接第一层金属布线和第二层金属布线的接触件相对应的位置处，而窄宽图案部分设置在与布线部分相对应的位置处第一层金属布线。在具有抗蚀剂图案的掩模的第二Al-Si-Cu膜层上施加第一蚀刻之后，在W膜层上施加第二蚀刻。此后，通过施加第三蚀刻，去除残留在第一层金属布线上的抗蚀剂图案，并将第一Al-Si-Cu膜层变形为高金属膜部分和短金属膜部分。在第一Al-Si-Cu膜层上积累层间绝缘膜层之后，在该层间绝缘膜层上施加回蚀，直到高金属膜部分的顶部露出。然后，在层间绝缘膜层上形成第二层金属布线，使得第二层金属布线与高金属膜部分连接。

2. 发明授权

US5576247A Thin layer forming method wherein hydrophobic molecular layers preventing a BPSG layer from absorbing moisture 失效
标题翻译：疏水分子层防止BPSG层吸收水分的薄层形成方法
公开(公告)号：US5576247A
公开(公告)日：1996-11-19
申请号：US97231
申请日：1993-07-27
申请人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
发明人： Kousaku Yano , Masayuki Endo , Yuka Terai , Noboru Nomura , Tomoyasu Murakami , Tetsuya Ueda , Satoshi Ueda
IPC分类号： H01L21/3105 , H01L21/316
CPC分类号： H01L21/3105 , Y10S438/974
摘要： A BPSG layer serving as a silicon oxide layer is formed on a semiconductor substrate 1. Formed on the surface of the BPSG layer is a hydrophobic molecular layer comprising hydrophobic groups such as methyl, ethyl and the like, by a silylation reaction (in which silyl having hydrophobic groups such as methyl groups, ethyl groups and the like, is reacted with OH groups, and in which the hydrophobic groups are substituted with H of the OH groups to generate --O--Si(CH.sub.3).sub.3 or the like). The molecular layer prevents the BPSG layer from absorbing moisture.
摘要翻译：在半导体衬底1上形成用作氧化硅层的BPSG层。在BPSG层的表面上形成疏水性分子层，其通过甲硅烷基化反应（甲基，具有疏水基团如甲基，乙基等与OH基团反应，并且其中疏水基团被H的OH基团取代以产生-O-Si（CH 3）3等）。分子层防止BPSG层吸湿。

3. 发明授权

US5986313A Semiconductor device comprising MISFETS and method of manufacturing the same 失效
标题翻译：包括MISFET的半导体器件及其制造方法
公开(公告)号：US5986313A
公开(公告)日：1999-11-16
申请号：US988776
申请日：1997-12-11
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for ccntact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准来形成用于与有源区域成反射的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

4. 发明授权

US5733812A Semiconductor device with a field-effect transistor having a lower resistance impurity diffusion layer, and method of manufacturing the same 失效
标题翻译：具有具有较低电阻杂质扩散层的场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5733812A
公开(公告)日：1998-03-31
申请号：US571131
申请日：1995-12-12
申请人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
发明人： Tetsuya Ueda , Takashi Uehara , Kousaku Yano , Satoshi Ueda
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/417 , H01L21/265
CPC分类号： H01L29/6659 , H01L21/823475 , H01L29/41775 , H01L29/41783 , H01L29/66545
摘要： There is formed an isolation which surrounds an active region of a semiconductor substrate. Formed over the active region and on the isolation, respectively, are a gate electrode and two gate interconnections on both sides thereof. Between the gate electrode and the gate interconnections are located two first interspaces each of which is smaller in width than a specified value and a second interspace which is larger in width than the specified value and interposed between the two first interspaces. In forming side walls on both side faces of the gate electrode and gate interconnections by depositing an insulating film on the substrate, the first interspaces are buried with the insulating film. Thereafter, a metal film is deposited on the substrate, followed by chemical mechanical polishing till the gate electrode, gate interconnections, and side walls become exposed. By the process, withdrawn electrodes from a source/drain region for contact with the active region is formed by self alignment, while the withdrawn electrodes are insulated from the gate electrode and gate interconnections by the side walls.
摘要翻译：形成围绕半导体衬底的有源区的隔离。分别在有源区和隔离层上形成栅电极和两侧栅极互连。在栅极电极和栅极互连之间设置两个第一空间，每个空间的宽度小于指定值，第二空间的宽度大于指定值并插入在两个第一间隙之间。在通过在衬底上沉积绝缘膜来形成栅电极的两个侧面上的侧壁和栅极互连时，第一间隙被绝缘膜掩埋。然后，将金属膜沉积在基板上，然后进行化学机械抛光，直到栅极，栅极互连和侧壁变得暴露。通过该处理，通过自对准形成来自用于与有源区接触的源极/漏极区域的引出电极，而引出的电极通过侧壁与栅电极和栅极互连绝缘。

5. 发明授权

US5545919A Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5545919A
公开(公告)日：1996-08-13
申请号：US497756
申请日：1995-07-03
申请人： Satoshi Ueda , Tetsuya Ueda , Atsuhiro Yamano , Kousaku Yano
发明人： Satoshi Ueda , Tetsuya Ueda , Atsuhiro Yamano , Kousaku Yano
IPC分类号： H01L21/31 , H01L21/316 , H01L21/318 , H01L23/31 , H01L23/52 , H01L23/532 , H01L23/58
CPC分类号： H01L23/3171 , H01L23/5329 , H01L2924/0002
摘要： Metal wires are formed side by side over a semiconductor substrate, with an interlayer insulating film interposed between the metal interconnections and the semiconductor substrate. The metal interconnections are covered with a passivation film composed of a lower silicon oxide film and an upper silicon nitride film. The silicon oxide film is deposited so that the maximum thickness of the portions of the silicon oxide film on the side faces of the metal interconnections is less than half of the minimum space between the metal interconnections. The silicon nitride film is deposited so as to be interposed between the portions of the silicon oxide film on the side faces of the adjacent metal interconnections.
摘要翻译：金属线并排地形成在半导体衬底上，层间绝缘膜介于金属互连和半导体衬底之间。金属互连用由下部氧化硅膜和上部氮化硅膜构成的钝化膜覆盖。沉积氧化硅膜，使得金属互连侧面上的氧化硅膜的部分的最大厚度小于金属互连之间的最小空间的一半。沉积氮化硅膜以便在相邻的金属互连的侧面上介于氧化硅膜的部分之间。

6. 发明授权

US5760429A Multi-layer wiring structure having varying-sized cutouts 失效
标题翻译：具有不同大小的切口的多层布线结构
公开(公告)号：US5760429A
公开(公告)日：1998-06-02
申请号：US834303
申请日：1997-02-18
申请人： Kousaku Yano , Tetsuya Ueda
发明人： Kousaku Yano , Tetsuya Ueda
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L23/5226 , H01L21/76805 , H01L2924/0002
摘要： An integrated circuit having a multi-layered metal wiring structure with interlayer insulating films therebetween. A small cutout is made in a metal wiring when it is desirous to have the metal wiring touch a contact formed in a through hole passing through said cutout. A larger cutout is made in a metal wiring when it is desirous to have the metal wiring remain spaced from a contact formed in a through hole passing through said cutout.
摘要翻译：一种集成电路，具有在其间具有层间绝缘膜的多层金属布线结构。当希望金属布线接触通过所述切口的通孔中形成的触点时，在金属布线中形成小切口。当希望金属布线保持与通过所述切口的通孔中形成的触点间隔开时，在金属布线中形成较大的切口。

7. 发明授权

US08669833B2 Three-dimensional metamaterial having function of allowing and inhibiting propagation of electromagnetic waves 有权
标题翻译：具有允许和禁止电磁波传播的功能的三维超材料
公开(公告)号：US08669833B2
公开(公告)日：2014-03-11
申请号：US13375945
申请日：2010-06-03
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01P1/205 , H01P7/10
CPC分类号： H01P7/10 , G02B1/002 , G02B5/3058 , H01P1/20 , H01P1/2084
摘要： In a metamaterial, a dielectric layer includes a host medium and dielectric bodies disposed in rows with predetermined intervals therebetween is sandwiched between a pair of conductive mesh plates each having holes, thereby forming a functional layer including dielectric resonators corresponding to the dielectric bodies. The metamaterial is configured by laminating the functional layers. The holes and the dielectric resonators are positioned coaxially and an electromagnetic wave is propagated in each of the functional layers in a propagation direction perpendicular to a multi-layered laminate surface such that the metamaterial function as a left-handed metamaterial in relation to the propagation direction perpendicular to the multi-layered surface.
摘要翻译：在超材料中，电介质层包括主介体，并且以一定间隔设置成行的电介质体夹在一对具有孔的导电网板之间，从而形成包括对应于介电体的介电谐振器的功能层。超材料通过层压功能层而构成。孔和介质谐振器同轴地定位，并且电磁波在垂直于多层叠层表面的传播方向上在每个功能层中传播，使得超材料相对于传播方向作为左旋超材料垂直于多层表面。

8. 发明授权

US08294538B2 Transmission line microwave apparatus including at least one non-reciprocal transmission line part between two parts 有权
标题翻译：传输线微波装置包括两部分之间的至少一个不可逆传输线部分
公开(公告)号：US08294538B2
公开(公告)日：2012-10-23
申请号：US12530102
申请日：2008-03-05
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01P3/08
CPC分类号： H01Q1/38 , H01P1/203 , H01P1/207 , H01P1/32 , H01Q13/206
摘要： A transmission line microwave apparatus includes at least one nonreciprocal transmission line part, which includes a series branch circuit equivalently including a capacitive element and a shunt branch circuit equivalently including an inductive element. The nonreciprocal transmission line part has gyrotropic characteristic by being magnetized in a magnetization direction different from the propagation direction of a microwave, and has an asymmetric structure to a plane formed by the propagation direction and the magnetization direction. The nonreciprocal transmission line part has a propagation constant and an operating frequency set in a dispersion curve that represents a relation between the propagation constant and the operating frequency so that the propagation constant in the forward direction and the propagation constant in the backward direction have nonreciprocal phase characteristics different from each other. A microwave transmission line is constituted by cascade-connecting at least one non-reciprocal transmission line part between first and second ports.
摘要翻译：传输线微波装置包括至少一个不可逆传输线部分，其包括等效地包括电容元件的串联分支电路和等效地包括电感元件的分流分支电路。不可逆传输线部分通过在与微波的传播方向不同的磁化方向上磁化而具有陀螺特性，并且具有与由传播方向和磁化方向形成的平面不对称的结构。不可逆传输线部分具有传播常数和在表示传播常数与工作频率之间的关系的色散曲线中设定的工作频率，使得正向传播常数和反向传播常数具有非相互相位特征彼此不同。微波传输线通过级联连接第一和第二端口之间的至少一个不可逆传输线部分而构成。

9. 发明授权

US08034707B2 Method for fabricating semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US08034707B2
公开(公告)日：2011-10-11
申请号：US12897416
申请日：2010-10-04
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L21/76802 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes the steps of forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在第一绝缘膜中间隔地形成多个下互连; 去除位于下互连之间的第一绝缘膜的一部分，从而形成互连互连间隙; 在所述第一绝缘膜上形成第二绝缘膜，其中所述下互连和互连互连间隙形成为使得从所述互连互连间隙形成气隙; 以及在所述第二绝缘膜中形成连接到所述下部互连中的一个的连接部分和连接到所述连接部分的上部互连件。连接部分形成为连接到不邻近气隙的下互连中的一个。

10. 发明授权

US07622807B2 Semiconductor device with a low dielectric constant film between lower interconnections 有权
标题翻译：在低互连之间具有低介电常数膜的半导体器件
公开(公告)号：US07622807B2
公开(公告)日：2009-11-24
申请号：US12277933
申请日：2008-11-25
申请人： Tetsuya Ueda
发明人： Tetsuya Ueda
IPC分类号： H01L29/40
CPC分类号： H01L21/76801 , H01L21/76802 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method for fabricating a semiconductor device includes the steps of: forming a plurality of lower interconnections at intervals in a first insulating film; removing a portion of the first insulating film located between the lower interconnections, thereby forming an interconnection-to-interconnection gap; forming a second insulating film over the first insulating film in which the lower interconnections and the interconnection-to-interconnection gap are formed such that an air gap is formed out of the interconnection-to-interconnection gap; and forming, in the second insulating film, a connection portion connected to one of the lower interconnections and an upper interconnection connected to the connection portion. The connection portion is formed to be connected to one of the lower interconnections not adjacent to the air gap.
摘要翻译：一种制造半导体器件的方法包括以下步骤：在第一绝缘膜中间隔地形成多个下互连; 去除位于下互连之间的第一绝缘膜的一部分，从而形成互连互连间隙; 在所述第一绝缘膜上形成第二绝缘膜，其中所述下互连和互连互连间隙形成为使得从所述互连互连间隙形成气隙; 以及在所述第二绝缘膜中形成连接到所述下部互连中的一个的连接部分和连接到所述连接部分的上部互连件。连接部分形成为连接到不邻近气隙的下互连中的一个。

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