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1. 发明授权

US5702956A Test site and a method of monitoring via etch depths for semiconductor devices 失效
标题翻译：测试点和通过半导体器件的蚀刻深度监测的方法
公开(公告)号：US5702956A
公开(公告)日：1997-12-30
申请号：US703086
申请日：1996-08-26
申请人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
发明人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , H01L22/12
摘要： The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.
摘要翻译：本发明提供了用于通过蚀刻深度测量的产品晶片上的测试位置以及使用测试部位监测通孔的深度的方法。提供具有测试位置区域和电路区域的衬底。试验场地通过形成试验场地。测试点通孔用于测量残留在测试部位的绝缘层的深度和测试部位通孔的深度。测量正在使用在线不可破坏的测量工具，例如椭偏仪或分光光度计。测试地点专门设计为足够大，以便通过在线测量工具测量通孔深度。在通孔蚀刻之后测量残留在测试部位通孔中的氧化物的深度，并且与从电路区域中的金属线的顶部去除的氮化钛的量相关。然后调整通孔蚀刻工艺以使通孔蚀刻在最佳点处居中，以确保足够的通孔足够深，而不会在金属线上去除太多的顶部阻挡层（例如氮化钛）膜。

2. 发明授权

US5900644A Test site and a method of monitoring via etch depths for semiconductor devices 失效
标题翻译：测试点和通过半导体器件的蚀刻深度监测的方法
公开(公告)号：US5900644A
公开(公告)日：1999-05-04
申请号：US892214
申请日：1997-07-14
申请人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
发明人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
IPC分类号： H01L21/768 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L21/76816
摘要： The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.
摘要翻译：本发明提供了用于通过蚀刻深度测量的产品晶片上的测试位置以及使用测试部位监测通孔的深度的方法。提供具有测试位置区域和电路区域的衬底。试验场地通过形成试验场地。测试点通孔用于测量残留在测试部位的绝缘层的深度和测试部位通孔的深度。测量正在使用在线不可破坏的测量工具，例如椭偏仪或分光光度计。测试地点特别设计成足够大，可以通过在线测量工具测量通孔深度。在通孔蚀刻之后测量残留在测试部位通孔中的氧化物的深度，并且与从电路区域中的金属线的顶部去除的氮化钛的量相关。然后调整通孔蚀刻工艺以使通孔蚀刻在最佳点处居中，以确保足够的通孔足够深，而不会在金属线上去除太多的顶部阻挡层（例如氮化钛）膜。

3. 发明授权

US08653664B2 Barrier layers for copper interconnect 有权
标题翻译：铜互连屏障层
公开(公告)号：US08653664B2
公开(公告)日：2014-02-18
申请号：US12832790
申请日：2010-07-08
申请人： Nai-Wei Liu , Zhen-Cheng Wu , Cheng-Lin Huang , Po-Hsiang Huang , Yung-Chih Wang , Shu-Hui Su , Dian-Hau Chen , Yuh-Jier Mii
发明人： Nai-Wei Liu , Zhen-Cheng Wu , Cheng-Lin Huang , Po-Hsiang Huang , Yung-Chih Wang , Shu-Hui Su , Dian-Hau Chen , Yuh-Jier Mii
IPC分类号： H01L23/522 , H01L21/44
CPC分类号： H01L21/76846 , H01L21/76831 , H01L21/76864 , H01L21/76867 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A copper interconnect includes a copper layer formed in a dielectric layer, having a first portion and a second portion. A first barrier layer is formed between the first portion of the copper layer and the dielectric layer. A second barrier layer is formed at the boundary between the second portion of the copper layer and the dielectric layer. The first barrier layer is a dielectric layer, and the second barrier layer is a metal oxide layer.
摘要翻译：铜互连包括形成在电介质层中的铜层，具有第一部分和第二部分。在铜层的第一部分和电介质层之间形成第一阻挡层。在铜层的第二部分和电介质层之间的边界处形成第二阻挡层。第一阻挡层是电介质层，第二阻挡层是金属氧化物层。

4. 发明授权

US08524570B2 Method and apparatus for improving gate contact 有权
标题翻译：改善栅极接触的方法和装置
公开(公告)号：US08524570B2
公开(公告)日：2013-09-03
申请号：US12890995
申请日：2010-09-27
申请人： Harry Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
发明人： Harry Hak-Lay Chuang , Chih-Yang Yeh , Bao-Ru Young , Yuh-Jier Mii
IPC分类号： H01L21/76
CPC分类号： H01L29/78 , H01L21/76224 , H01L21/76232 , H01L21/823456 , H01L21/823475 , H01L21/823481 , H01L27/088
摘要： A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess.
摘要翻译：一种制造半导体器件的方法包括提供具有第一表面的衬底，形成部分地设置在衬底中的隔离结构，并且具有高于第一表面的第二表面，台阶高度，去除隔离结构的一部分以形成在其中具有设置在第一表面下方的底表面的凹槽，以及形成在凹部上方接合栅极结构的触点。不同的方面涉及一种装置，其包括具有第一表面的衬底，部分地设置在衬底中的隔离结构，并且具有比第一表面高的台阶高度的第二表面;从第二表面向下延伸的凹部，凹部具有设置在第一表面下方的底表面，栅极结构，以及在凹部上接合栅极结构的触点。

5. 发明申请

US20080043561A1 CIRCUIT FOR AN SRAM WITH REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的SRAM的电路
公开(公告)号：US20080043561A1
公开(公告)日：2008-02-21
申请号：US11506438
申请日：2006-08-18
申请人： Ping-Wei Wang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Yuh-Jier Mii
IPC分类号： G11C5/14 , G11C11/00 , G11C8/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit is provided coupled to the lower power supply and outputting a higher supply voltage. An array of SRAM memory cells that may comprise 4 T, 6 T or 8 T static RAM memory cells are coupled to the higher supply voltage during read and write operations. Operating the peripheral circuitry of the SRAM memory at the lower supply voltage achieves reduced power consumption for the SRAM memory and the integrated circuit.
摘要翻译：一种用于提供具有降低功耗的SRAM存储器的电路和方法，该SRAM存储器特别适用于将具有其他逻辑和存储器功能的SRAM存储器嵌入集成电路中。向SRAM存储器的外围电路提供较低的电源电压。提供电平移位器电路，耦合到下电源并输出较高的电源电压。可以包括4T，6T或8T静态RAM存储器单元的SRAM存储器单元的阵列在读取和写入操作期间耦合到更高的电源电压。在较低电源电压下操作SRAM存储器的外围电路实现了SRAM存储器和集成电路的功耗降低。

6. 发明授权

US09123553B2 Method and system for bonding 3D semiconductor device 有权
标题翻译：三维半导体器件接合方法及系统
公开(公告)号：US09123553B2
公开(公告)日：2015-09-01
申请号：US13269260
申请日：2011-10-07
申请人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
发明人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
IPC分类号： H01L21/00 , H01L25/065 , H01L21/683 , H01L21/768 , H01L23/00 , H01L25/00
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/6836 , H01L21/762 , H01L21/76898 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/05553 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.
摘要翻译：一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

7. 发明申请

US20110068400A1 Methods and Apparatus for SRAM Bit Cell with Low Standby Current, Low Supply Voltage and High Speed 有权
标题翻译：具有低待机电流，低电源电压和高速的SRAM位单元的方法和装置
公开(公告)号：US20110068400A1
公开(公告)日：2011-03-24
申请号：US12748098
申请日：2010-03-26
申请人： Ping-Wei Wang , Chang-Ta Yang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Chang-Ta Yang , Yuh-Jier Mii
IPC分类号： H01L27/12 , H01L29/78
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116
摘要： Circuits and methods for providing an SRAM or CAM bit cell. In one embodiment, a bit cell portion with thicker gate oxides in the storage cell transistors, and thinner gate oxides in a read port section having transistors are disclosed. The use of the thick gate oxides in the storage cell transistors provides a stable storage of data and lower standby leakage current. The use of the thinner gate oxides in the read port transistors provides fast read accesses and allows a lower Vcc,min in the read port. The methods used to form the dual gate oxide thickness SRAM cells have process steps compatible with the existing semiconductor manufacturing processes. Embodiments using high k gate dielectrics, dual gate dielectric materials in a single bit cell, and using finFET and planar devices in a bit cell are described. Methods for forming the structures are disclosed.
摘要翻译：用于提供SRAM或CAM位单元的电路和方法。在一个实施例中，公开了存储单元晶体管中具有较厚栅极氧化物的位单元部分，以及具有晶体管的读取端口部分中较薄的栅极氧化物。在存储单元晶体管中使用厚栅极氧化物提供数据的稳定存储和较低待机漏电流。在读端口晶体管中使用较薄的栅极氧化物提供快速的读取访问，并允许在读取端口中较低的Vcc，min。用于形成双栅极氧化物厚度SRAM单元的方法具有与现有半导体制造工艺兼容的工艺步骤。描述了在单个位单元中使用高k栅极电介质，双栅介质材料以及在位单元中使用finFET和平面器件的实施例。公开了形成结构的方法。

8. 发明授权

US07436696B2 Read-preferred SRAM cell design 有权
标题翻译：读取优先的SRAM单元设计
公开(公告)号：US07436696B2
公开(公告)日：2008-10-14
申请号：US11582116
申请日：2006-10-17
申请人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
发明人： Ping-Wei Wang , Yuh-Jier Mii , Hung-Jen Liao
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/26586 , H01L29/66659
摘要： A read-preferred SRAM cell includes a pull-up MOS device having a first drive current, a pull-down MOS device coupled to the pull-up MOS device, the pull-down MOS device having a second drive current, and a pass-gate MOS device having a third drive current coupled to the pull-up MOS device and the pull-down MOS device. The first drive current and the third drive current preferably have an α ratio of between about 0.5 and about 1. The second drive current and the third drive current preferably have a β ratio of between about 1.45 and 5.
摘要翻译：读优选SRAM单元包括具有第一驱动电流的上拉MOS器件，耦合到上拉MOS器件的下拉MOS器件，具有第二驱动电流的下拉MOS器件，栅极MOS器件具有耦合到上拉MOS器件和下拉MOS器件的第三驱动电流。第一驱动电流和第三驱动电流优选地具有在约0.5和约1之间的α比率。第二驱动电流和第三驱动电流优选具有在约1.45和5之间的β比率。

9. 发明授权

US07359272B2 Circuit and method for an SRAM with reduced power consumption 有权
标题翻译：具有降低功耗的SRAM的电路和方法
公开(公告)号：US07359272B2
公开(公告)日：2008-04-15
申请号：US11506438
申请日：2006-08-18
申请人： Ping-Wei Wang , Yuh-Jier Mii
发明人： Ping-Wei Wang , Yuh-Jier Mii
IPC分类号： G11C7/00
CPC分类号： G11C11/413 , G11C8/08
摘要： A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circuitry for the SRAM memory. A level shifter circuit is provided coupled to the lower power supply and outputting a higher supply voltage. An array of SRAM memory cells that may comprise 4T, 6T or 8T static RAM memory cells are coupled to the higher supply voltage during read and write operations. Operating the peripheral circuitry of the SRAM memory at the lower supply voltage achieves reduced power consumption for the SRAM memory and the integrated circuit.
摘要翻译：一种用于提供具有降低功耗的SRAM存储器的电路和方法，该SRAM存储器特别适用于将具有其他逻辑和存储器功能的SRAM存储器嵌入集成电路中。向SRAM存储器的外围电路提供较低的电源电压。提供电平移位器电路，耦合到下电源并输出较高的电源电压。可以包括4T，6T或8T静态RAM存储器单元的SRAM存储器单元的阵列在读取和写入操作期间耦合到更高的电源电压。在较低电源电压下操作SRAM存储器的外围电路实现了SRAM存储器和集成电路的功耗降低。

10. 发明授权

US6114747A Process design for wafer edge in VLSI 有权
标题翻译： VLSI晶圆边缘的工艺设计
公开(公告)号：US6114747A
公开(公告)日：2000-09-05
申请号：US378500
申请日：1999-08-20
申请人： Zin-Chein Wei , Yuh-Jier Mii
发明人： Zin-Chein Wei , Yuh-Jier Mii
IPC分类号： H01L21/00 , H01L23/31 , H01L23/544 , H01L23/58 , H01L29/06
CPC分类号： H01L21/6715 , H01L23/3192 , H01L2924/0002
摘要： A wafer structure and method of forming a wafer structure with all of the dielectric material and conducting material films removed from the outer periphery of the wafer in order to protect the dielectric and conducting films from damage due to wafer handling, storage, or clamping. The dielectric or conducting material is removed from the wafer edge using wafer edge exposure or edge bead rinse methods. The wafer edge exposure method is carried out at the same time the dielectric or conducting layer is being patterned.
摘要翻译：一种晶片结构和方法，其形成具有从晶片的外周边移除的所有电介质材料和导电材料膜的晶片结构，以便保护电介质和导电膜免受由于晶片处理，存储或夹紧的损坏。使用晶片边缘曝光或边缘珠冲洗方法从晶片边缘去除电介质或导电材料。晶片边缘曝光方法是在电介质层或导电层被图案化的同时进行的。

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