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1. 发明授权

US09123553B2 Method and system for bonding 3D semiconductor device 有权
标题翻译：三维半导体器件接合方法及系统
公开(公告)号：US09123553B2
公开(公告)日：2015-09-01
申请号：US13269260
申请日：2011-10-07
申请人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
发明人： Chung-Shi Liu , Chen-Hua Yu , Yuh-Jier Mii , Yuan-Chen Sun
IPC分类号： H01L21/00 , H01L25/065 , H01L21/683 , H01L21/768 , H01L23/00 , H01L25/00
CPC分类号： H01L21/50 , H01L21/6835 , H01L21/6836 , H01L21/762 , H01L21/76898 , H01L24/95 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2221/68327 , H01L2221/68354 , H01L2224/05553 , H01L2224/16 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73265 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/14 , H01L2924/00 , H01L2924/00014
摘要： A method and system and for fabricating 3D (three-dimensional) SIC (stacked integrated chip) semiconductor devices. The system includes a vacuum chamber, a vacuum-environment treatment chamber, and a bonding chamber, though in some embodiments the same physical enclosure may serve more than one of these functions. A vacuum-environment treatment source in communication with the vacuum-environment treatment chamber provides a selected one or more of a hydrogen (H2)-based thermal anneal, an H2-based plasma treatment, or an ammonia (NH3)-based plasma treatment. In another embodiment, a method includes placing a semiconductor chip in a vacuum environment, performing a selected vacuum-environment treatment, and bonding the chip to a base wafer. A plurality of chips formed as dice on a semiconductor wafer may, of course, be simultaneously treated and bonded in this way as well, either before or after dicing.
摘要翻译：一种用于制造3D（三维）SIC（堆叠集成芯片）半导体器件的方法和系统。该系统包括真空室，真空环境处理室和粘合室，尽管在一些实施例中，相同的物理外壳可以用于这些功能中的一种以上。与真空环境处理室连通的真空环境处理源提供基于氢（H 2）的热退火，基于H 2的等离子体处理或基于氨（NH 3）的等离子体处理中的一种或多种。在另一个实施例中，一种方法包括将半导体芯片放置在真空环境中，执行所选择的真空环境处理，以及将芯片接合到基底晶片。在半导体晶片上形成为多个芯片的多个芯片当然可以在切割之前或之后以这种方式同时进行处理和粘合。

2. 发明申请

US20080042123A1 Methods for controlling thickness uniformity of SiGe regions 审中-公开
标题翻译：控制SiGe区域厚度均匀性的方法
公开(公告)号：US20080042123A1
公开(公告)日：2008-02-21
申请号：US11699611
申请日：2007-01-30
申请人： Kong-Beng Thei , Harry Chuang , Yuan-Chen Sun
发明人： Kong-Beng Thei , Harry Chuang , Yuan-Chen Sun
IPC分类号： H01L31/00
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit includes a semiconductor substrate having a first region, at least one p-type region in the semiconductor substrate having SiGe regions formed therein, and at least one n-type region in the semiconductor substrate. All SiGe regions in the first region have a first combined area. All p-type regions in the first region have a second combined area. All n-type regions in the first region have a third combined area. The ratio of the first combined area to a total area of the second combined area and the third combined area is less than about 30 percent.
摘要翻译：集成电路包括具有第一区域的半导体衬底，在其中形成有SiGe区域的半导体衬底中的至少一个p型区域和半导体衬底中的至少一个n型区域。第一个地区的所有SiGe地区都有第一个合并区域。第一区域中的所有p型区域具有第二组合区域。第一个区域的所有n型区域都有第三个合并区域。第一组合面积与第二组合面积和第三组合面积的总面积的比例小于约30％。

3. 发明授权

US6083824A Borderless contact 失效
标题翻译：无边界联络
公开(公告)号：US6083824A
公开(公告)日：2000-07-04
申请号：US114132
申请日：1998-07-13
申请人： Chao-Chieh Tsai , Chin-Hsiung Ho , Yuan-Chen Sun
发明人： Chao-Chieh Tsai , Chin-Hsiung Ho , Yuan-Chen Sun
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76811 , H01L21/31144 , H01L21/76877
摘要： A method of forming borderless contacts and vias is disclosed. Borders which are conventionally provided in aligning contacts and vias to device and/or metal regions in a semiconductor device take up too much valuable real estate on semiconductor substrates, and hence reduce productivity of the products. By employing a hard-mask of this invention, and a specific sequence of process steps, alignment can be achieved without the need for borders. First, a thin nitride layer is deposited on an insulating layer formed over a substructure of a substrate having device and/or metal regions. The hard-mask is patterned with metal line openings, and a photoresist layer is formed with contact or via pattern over the already patterned hard-mask. The contact/via openings are etched into the dielectric layer until the substructure is reached. The hole openings are filled plug metal and then partially etched back, leaving a plug in the hole opening. The line trench is etched further into the dielectric layer until metal plug is reached. The trench is then filled with metal, such as aluminum-copper or copper and the excess is removed by chemical-mechanical polishing. Thus, a borderless and self-aligned interconnect comprising plug and metal line is formed.
摘要翻译：公开了一种形成无边界接触和通孔的方法。通常设置在半导体器件中的器件和/或金属区域中的对齐触点和通孔的边界在半导体衬底上占据太多有价值的空间，因此降低了产品的生产率。通过采用本发明的硬掩模和工艺步骤的特定顺序，可以实现对准而不需要边界。首先，将薄的氮化物层沉积在形成在具有器件和/或金属区域的衬底的子结构之上的绝缘层上。硬掩模用金属线开口图案化，并且在已经图案化的硬掩模上形成具有接触或通孔图案的光致抗蚀剂层。将接触/通孔开口蚀刻到电介质层中，直到达到底层结构。孔开口是填充塞子金属，然后部分地被回蚀，留下孔中的塞子。将线沟槽进一步蚀刻到电介质层中，直到达到金属插塞。然后用金属填充沟槽，例如铝 - 铜或铜，并且通过化学机械抛光除去多余的。因此，形成包括插头和金属线的无边界和自对准互连。

4. 发明授权

US5801444A Multilevel electronic structures containing copper layer and copper-semiconductor layers 失效
标题翻译：含铜层和铜半导体层的多层电子结构
公开(公告)号：US5801444A
公开(公告)日：1998-09-01
申请号：US756829
申请日：1996-11-20
申请人： Mohamed Osama Aboelfotoh , Lia Krusin-Elbaum , Yuan-Chen Sun
发明人： Mohamed Osama Aboelfotoh , Lia Krusin-Elbaum , Yuan-Chen Sun
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/485 , H01L23/532 , H01L29/45 , H01L29/47 , H01L29/49 , H01L23/48
CPC分类号： H01L21/76877 , H01L21/2807 , H01L21/28512 , H01L21/28518 , H01L21/76838 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/7685 , H01L21/76855 , H01L23/485 , H01L23/53228 , H01L23/53238 , H01L29/456 , H01L29/47 , H01L29/4966 , H01L29/4975 , H01L2924/0002
摘要： A low temperature annealed Cu silicide or germanide layer on the surface of a single crystalline semiconductor substrate of Si or Ge is used in interconnection metallization for integrated circuits. The Cu silicide or germanide layer is preferably formed by heating Cu deposited on a Si or Ge substrate up to about 200.degree. C. for about 30 minutes. The layer demonstrates superior (near ideal) current/voltage characteristics and can be used as a high temperature (600-800.degree. C.) stable Ohmic/Schottky contact to Si or as a Cu diffusion barrier. Additional embodiments involve a Cu layer on a Ge layer on Si substrate, a Cu layer on a Si.sub.x Ge.sub.1-x layer on a substrate, and the use of an intermediate layer of a refractory metal such as W.
摘要翻译：在Si或Ge的单晶半导体衬底的表面上的低温退火的Cu硅化物或锗化物层用于集成电路的互连金属化。 Cu硅化物或锗化锗层优选通过将沉积在Si或Ge衬底上的Cu加热至约200℃形成约30分钟。该层表现出优异的（接近理想的）电流/电压特性，并且可以用作与Si或作为Cu扩散阻挡层的高温（600-800℃）稳定的欧姆/肖特基接触。另外的实施方案涉及Si衬底上Ge层上的Cu层，衬底上六Ge1-x层上的Cu层，以及使用难熔金属如W的中间层。

5. 发明授权

US5117271A Low capacitance bipolar junction transistor and fabrication process therfor 失效
标题翻译：低电容双极性晶体管和制造工艺
公开(公告)号：US5117271A
公开(公告)日：1992-05-26
申请号：US624018
申请日：1990-12-07
申请人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
发明人： James H. Comfort , Tze-Chiang Chen , Pong-Fei Lu , Bernard S. Meyerson , Yuan-Chen Sun , Denny D. Tang
IPC分类号： H01L29/73 , H01L21/285 , H01L21/331 , H01L21/762 , H01L29/732
CPC分类号： H01L29/66287 , H01L21/28525 , H01L21/76229 , H01L29/66242
摘要： This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device. The last mentioned oxide layer starts out early in the fabrication process as a layer of oxidizable material, preferable polycrystalline silicon, which, at later steps in the process, acts as an etch-stop in its unoxidized state and as a memory element and mask in its oxidized state when a self-aligned datum element is removed and the thus exposed underlying dielectric elements must be removed to provide a planar emitter opening. The resulting transistor includes a planar emitter-emitter contact interface which provides for fine control of emitter depth in the underlying intrinsic base region.

6. 发明授权

US5461250A SiGe thin film or SOI MOSFET and method for making the same 失效
标题翻译： SiGe薄膜或SOI MOSFET及其制造方法
公开(公告)号：US5461250A
公开(公告)日：1995-10-24
申请号：US927901
申请日：1992-08-10
申请人： Joachim N. Burghartz , Bernard S. Meyerson , Yuan-Chen Sun
发明人： Joachim N. Burghartz , Bernard S. Meyerson , Yuan-Chen Sun
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786 , H01L27/12
CPC分类号： H01L29/66742 , H01L29/78648 , H01L29/78687
摘要： A dual gate thin film or SOI MOSFET device having a sufficiently thin body thickness with one or more semiconductor channel layer(s) sandwiched by semiconductor layers having a different energy band structure to automatically confine carriers to the channel layer(s) without the need for channel grading or modulation doping. Preferred embodiments employ strained layer epitaxy having Si/SiGe/Si or SiGe/Si/SiGe semiconductor layers.
摘要翻译：具有足够薄的体厚度的双栅极薄膜或SOI MOSFET器件，其中一个或多个半导体沟道层被具有不同能带结构的半导体层夹在中间，以自动将载流子限制在沟道层上，而不需要信道分级或调制掺杂。优选实施例采用具有Si / SiGe / Si或SiGe / Si / SiGe半导体层的应变层外延。

7. 发明授权

US07612364B2 MOS devices with source/drain regions having stressed regions and non-stressed regions 有权
标题翻译：源极/漏极区域具有应力区域和非应力区域的MOS器件
公开(公告)号：US07612364B2
公开(公告)日：2009-11-03
申请号：US11602100
申请日：2006-11-20
申请人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
发明人： Harry Chuang , Kong-Beng Thei , Yuan-Chen Sun
IPC分类号： H01L29/06
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636
摘要： A semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack, wherein the stressor comprises an impurity of a first conductivity type; and a portion of the semiconductor substrate adjoining the stressor and on an opposite side of the stressor from the gate stack, wherein the portion of the semiconductor substrate is doped with an impurity of the first conductivity type.
摘要翻译：半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; 应力源，其具有至少一部分在所述半导体衬底中并且邻近所述栅叠层，其中所述应力源包括第一导电类型的杂质; 所述半导体衬底的与所述应力源相邻的部分以及所述应力源与所述栅极堆叠相反的一侧，其中所述半导体衬底的所述部分掺杂有所述第一导电类型的杂质。

8. 发明授权

US6020255A Dual damascene interconnect process with borderless contact 失效
标题翻译：双镶嵌互连工艺与无边界接触
公开(公告)号：US6020255A
公开(公告)日：2000-02-01
申请号：US114131
申请日：1998-07-13
申请人： Chao-Chieh Tsai , Chin-Hsiung Ho , Yuan-Chen Sun
发明人： Chao-Chieh Tsai , Chin-Hsiung Ho , Yuan-Chen Sun
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76807
摘要： A dual damascene process is disclosed for forming contact and via interconnects without borders. A nitride layer is first formed on a dielectric layer to function as a hard-mask. Metal line trench is first etched into the nitride layer and then into the dielectric layer. Then, a second photoresist layer is used to pattern contact or via hole over line trench opening and the dielectric layer is further etched through the line trench into the dielectric layer until the substructure of the substrate is reached. It is disclosed that by using the nitride layer as a hard-mask, the registration or alignment tolerance between the contact/via hole pattern and the metal line pattern can be relaxed substantially and not use a border as is conventionally practiced in order to assure proper registration between the patterns. The borderless interconnect is achieved by filling the composite line opening and the hole opening with metal and chemical mechanical polishing. The process enables cost reduction and productivity in the semiconductor manufacturing line.
摘要翻译：公开了用于形成无边界的接触和通孔互连的双镶嵌工艺。首先在电介质层上形成氮化物层作为硬掩模。首先将金属线沟槽蚀刻到氮化物层中，然后进入电介质层。然后，使用第二光致抗蚀剂层来在线沟槽开口上形成接触或通孔，并且通过线沟槽进一步将电介质层蚀刻到电介质层中，直到达到基底的子结构。公开了通过使用氮化物层作为硬掩模，可以基本上松弛接触/通孔图案和金属线图案之间的配准或对准公差，而不像以往那样使用边界，以确保正确注册之间的模式。无缝互连通过用金属和化学机械抛光填充复合线开口和孔开口来实现。该方法可以在半导体生产线上降低成本和提高生产效率。

9. 发明授权

US09153662B2 MOSFET with selective dopant deactivation underneath gate 有权
标题翻译：栅极下选择性掺杂剂失活的MOSFET
公开(公告)号：US09153662B2
公开(公告)日：2015-10-06
申请号：US13434630
申请日：2012-03-29
申请人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265
CPC分类号： H01L29/1041 , H01L21/26506 , H01L21/2658 , H01L29/1045 , H01L29/1608 , H01L29/66537 , H01L29/66545 , H01L29/66651 , H01L29/7833
摘要： A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.
摘要翻译：在衬底上制造金属氧化物半导体场效应晶体管（MOSFET）器件的方法包括用第一类掺杂剂掺杂MOSFET器件的沟道区。源极和漏极在衬底中形成具有第二类型的掺杂剂。选择性掺杂剂失活在MOSFET器件的栅极下方的区域中进行。

10. 发明申请

US20130256796A1 MOSFET WITH SLECTIVE DOPANT DEACTIVATION UNDERNEATH GATE 有权
标题翻译：具有选择性猝死的MOSFET在门下
公开(公告)号：US20130256796A1
公开(公告)日：2013-10-03
申请号：US13434630
申请日：2012-03-29
申请人： Dhanyakumar Mahaveer SATHAIYA , Kai-Chieh YANG , Wei-Hao WU , Ken-Ichi GOTO , Zhiqiang WU , Yuan-Chen SUN
发明人： Dhanyakumar Mahaveer SATHAIYA , Kai-Chieh YANG , Wei-Hao WU , Ken-Ichi GOTO , Zhiqiang WU , Yuan-Chen SUN
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1041 , H01L21/26506 , H01L21/2658 , H01L29/1045 , H01L29/1608 , H01L29/66537 , H01L29/66545 , H01L29/66651 , H01L29/7833
摘要： A method of fabricating a metal-oxide-semiconductor field-effect transistor (MOSFET) device on a substrate includes doping a channel region of the MOSFET device with dopants of a first type. A source and a drain are formed in the substrate with dopants of a second type. Selective dopant deactivation is performed in a region underneath a gate of the MOSFET device.
摘要翻译：在衬底上制造金属氧化物半导体场效应晶体管（MOSFET）器件的方法包括用第一类掺杂剂掺杂MOSFET器件的沟道区。源极和漏极在衬底中形成具有第二类型的掺杂剂。选择性掺杂剂失活在MOSFET器件的栅极下方的区域中进行。

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