专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5702956A Test site and a method of monitoring via etch depths for semiconductor devices 失效
标题翻译：测试点和通过半导体器件的蚀刻深度监测的方法
公开(公告)号：US5702956A
公开(公告)日：1997-12-30
申请号：US703086
申请日：1996-08-26
申请人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
发明人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , H01L22/12
摘要： The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.
摘要翻译：本发明提供了用于通过蚀刻深度测量的产品晶片上的测试位置以及使用测试部位监测通孔的深度的方法。提供具有测试位置区域和电路区域的衬底。试验场地通过形成试验场地。测试点通孔用于测量残留在测试部位的绝缘层的深度和测试部位通孔的深度。测量正在使用在线不可破坏的测量工具，例如椭偏仪或分光光度计。测试地点专门设计为足够大，以便通过在线测量工具测量通孔深度。在通孔蚀刻之后测量残留在测试部位通孔中的氧化物的深度，并且与从电路区域中的金属线的顶部去除的氮化钛的量相关。然后调整通孔蚀刻工艺以使通孔蚀刻在最佳点处居中，以确保足够的通孔足够深，而不会在金属线上去除太多的顶部阻挡层（例如氮化钛）膜。

2. 发明授权

US5900644A Test site and a method of monitoring via etch depths for semiconductor devices 失效
标题翻译：测试点和通过半导体器件的蚀刻深度监测的方法
公开(公告)号：US5900644A
公开(公告)日：1999-05-04
申请号：US892214
申请日：1997-07-14
申请人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
发明人： Shu-Lan Ying , Yuan-Chang Huang , Jue-Jye Chen , Yuh-Jier Mii
IPC分类号： H01L21/768 , H01L23/544 , H01L23/58
CPC分类号： H01L22/34 , H01L21/76816
摘要： The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.
摘要翻译：本发明提供了用于通过蚀刻深度测量的产品晶片上的测试位置以及使用测试部位监测通孔的深度的方法。提供具有测试位置区域和电路区域的衬底。试验场地通过形成试验场地。测试点通孔用于测量残留在测试部位的绝缘层的深度和测试部位通孔的深度。测量正在使用在线不可破坏的测量工具，例如椭偏仪或分光光度计。测试地点特别设计成足够大，可以通过在线测量工具测量通孔深度。在通孔蚀刻之后测量残留在测试部位通孔中的氧化物的深度，并且与从电路区域中的金属线的顶部去除的氮化钛的量相关。然后调整通孔蚀刻工艺以使通孔蚀刻在最佳点处居中，以确保足够的通孔足够深，而不会在金属线上去除太多的顶部阻挡层（例如氮化钛）膜。

3. 发明授权

US07744953B2 Method for forming self-cleaning coating comprising hydrophobically-modified particles 有权
标题翻译：用于形成包含疏水改性颗粒的自清洁涂层的方法
公开(公告)号：US07744953B2
公开(公告)日：2010-06-29
申请号：US11318566
申请日：2005-12-28
申请人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
发明人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
IPC分类号： B05D3/02
CPC分类号： B05D5/08 , Y10T428/2809
摘要： A method for forming self-cleaning coating comprising hydrophobically-modified particles. Micro- or nano-particles are treated with a hydrophobic agent and an additive to form larger particles with the hydrophobic agent and the additive bonded thereto. A binder or crosslinker is attached to the larger particles by forming chemical bonds with at least one of the additive, the hydrophobic agent, and the particles, thus forming a coating material capable of forming self-cleaning coating.
摘要翻译：一种形成包含疏水改性颗粒的自清洁涂层的方法。用疏水剂和添加剂处理微米或纳米颗粒以与疏水剂和添加剂结合的较大颗粒形成。通过与添加剂，疏水剂和颗粒中的至少一种形成化学键，粘合剂或交联剂附着到较大的颗粒上，从而形成能够形成自清洁涂层的涂料。

4. 发明申请

US20080081395A1 Wafer level package structure of optical-electronic device and method for making the same 失效
公开(公告)号：US20080081395A1
公开(公告)日：2008-04-03
申请号：US11984014
申请日：2007-11-13
申请人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
发明人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
IPC分类号： H01L31/18
CPC分类号： H01L27/14683 , H01L27/14618 , H01L27/14687 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.

5. 发明申请

US20080063797A1 Low stain and low mist adhesion coating 有权
标题翻译：低污染和低雾附着涂层
公开(公告)号：US20080063797A1
公开(公告)日：2008-03-13
申请号：US11976850
申请日：2007-10-29
申请人： Yuan-Chang Huang , Leng-Long Jou , Yuung-Ching Sheen , Yih-Her Chang , Chia-Lin Wen , Hsiao-Hua Wu
发明人： Yuan-Chang Huang , Leng-Long Jou , Yuung-Ching Sheen , Yih-Her Chang , Chia-Lin Wen , Hsiao-Hua Wu
IPC分类号： B05D5/12 , B05D1/12
CPC分类号： B05D5/08 , B08B17/06 , B08B17/065 , C04B41/009 , C04B41/4922 , Y10T428/31598 , C04B41/463 , C04B41/4853 , C04B41/4961 , C04B41/502 , C04B41/5072 , C04B33/00 , C04B28/182
摘要： A low stain and low mist adhesion coating. Micro- or nano-particles are treated with a hydrophobic agent and an additive to form larger microstructure with the hydrophobic agent and the additive bonded thereto forming a low stain and low mist adhesion coating material. A low stain and low mist adhesion coating formed from the material has a contact angle of at least 130°. In addition, the low stain and low mist adhesion coating has less than 60% mist adhesion area.
摘要翻译：低污染和低雾附着涂层。用疏水剂和添加剂处理微米或纳米颗粒以与疏水剂一起形成更大的微结构，并且结合到其上的添加剂形成低污点和低雾度粘附涂层材料。由该材料形成的低污渍和低雾附着涂层具有至少130°的接触角。此外，低污染和低雾度粘附涂层具有小于60％的雾粘附面积。

6. 发明授权

US07317235B2 Wafer level package structure of optical-electronic device and method for making the same 失效
标题翻译：光电子器件的晶圆级封装结构及其制造方法
公开(公告)号：US07317235B2
公开(公告)日：2008-01-08
申请号：US11082899
申请日：2005-03-18
申请人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
发明人： Yuan-Chang Huang , Tai-Hung Chen , Yao-Sheng Lin , Su-Tsai Lu
IPC分类号： H01L31/0203
CPC分类号： H01L27/14683 , H01L27/14618 , H01L27/14687 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/13 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A wafer level package structure of optical-electronic device and method for making the same are disclosed. The wafer level package structure of optical-electronic device is provided by employing a substrate whose surfaces have several optical sensitive areas and divided into individual package devices. The manufacture steps first involve providing a substrate with several chips whose surfaces have an optical sensitive area and bonding pads, and providing transparent layer whose surfaces have conductive circuits and scribe lines. Then the bonding pads bond to conductive circuits and a protection layer is formed on the chip to expose partly conductive circuits. Forming a conductive film on the protection layer and the conductive film contacts with the extending conductive circuits to form the wafer level package structure of optical-electronic device. At last, the transparent layer is diced according to scribe lines to form the individual package devices.
摘要翻译：公开了一种光电子器件的晶片级封装结构及其制造方法。光电子器件的晶片级封装结构通过采用其表面具有多个光敏区域并分成单个封装器件的衬底来提供。制造步骤首先涉及提供具有表面具有光敏区域和接合焊盘的几个芯片的基板，并且提供其表面具有导电电路和划线的透明层。然后，接合焊盘接合到导电电路，并且在芯片上形成保护层以暴露部分导电电路。在保护层上形成导电膜，并且导电膜与延伸的导电电路接触以形成光电子器件的晶片级封装结构。最后，根据划线对透明层进行切割，形成单独的封装装置。

7. 发明授权

US07154176B2 Conductive bumps with non-conductive juxtaposed sidewalls 有权
标题翻译：具有非导电并置侧壁的导电凸块
公开(公告)号：US07154176B2
公开(公告)日：2006-12-26
申请号：US10714277
申请日：2003-11-14
申请人： Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
发明人： Yuan-Chang Huang , Shyh-Ming Chang , Su-Chia Lu
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L24/11 , H01L24/12 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/83 , H01L2224/05026 , H01L2224/05567 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/114 , H01L2224/116 , H01L2224/13099 , H01L2224/16 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/838 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/0781 , H01L2924/14 , H01L2924/3025 , H01L2224/05099
摘要： A microelectronic structure having a substrate of multiple conductive bumps for contact with bond pads on an electronic substrate in the fabrication of a flip chip electronic assembly. Each of the conductive bumps includes a conductive layer which is absent from at least one sidewall of the bump to prevent the inadvertent formation of a short-circuiting electrical path between adjacent conductive bumps in the electronic assembly.
摘要翻译：一种微电子结构，其具有多个导电凸块的基板，用于在倒装芯片电子组件的制造中与电子基板上的接合焊盘接触。每个导电凸块包括导体层，该导电层不存在于凸起的至少一个侧壁中，以防止电子组件中相邻的导电凸块之间的短路电路无意形成。

8. 发明申请

US20060147829A1 Method for forming coating material and the material formed thereby 有权
标题翻译：用于形成涂层材料的方法及由此形成的材料
公开(公告)号：US20060147829A1
公开(公告)日：2006-07-06
申请号：US11318459
申请日：2005-12-28
申请人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
发明人： Yuan-Chang Huang , Yuung-Ching Sheen , Yih-Her Chang , Kuo-Feng Lo
IPC分类号： G03G9/00 , C09C1/36
CPC分类号： C09D7/69 , C08K3/36 , C08K9/02 , C08K9/04 , C08K9/06 , C09D7/61 , C09D7/67 , C09D7/68
摘要： A method for forming a coating material capable of forming a hydrophobic, microstructured surface. The method comprises treating micro or nano-particles particles with a hydrophobic agent and an additive to form larger particles with the hydrophobic agent bonded thereto. The invention also comprises the coating material thus formed.
摘要翻译：一种形成能形成疏水，微结构化表面的涂层材料的方法。该方法包括用疏水剂和添加剂处理微粒或纳米颗粒以形成与疏水剂结合的更大颗粒。本发明还包括如此形成的涂料。

9. 发明授权

US06211083B1 Use of a novel capped anneal procedure to improve salicide formation 有权
标题翻译：使用新型封端退火方法来改善自杀化合物的形成
公开(公告)号：US06211083B1
公开(公告)日：2001-04-03
申请号：US09550263
申请日：2000-04-17
申请人： Jiunn-Der Yang , Chaucer Chung , Yuan-Chang Huang
发明人： Jiunn-Der Yang , Chaucer Chung , Yuan-Chang Huang
IPC分类号： H01L214763
CPC分类号： H01L29/665 , H01L21/28518
摘要： A process for forming a low resistance, titanium disilicide layer, on regions of a MOSFET device, has been developed. The process features the deposition of a capping, silicon oxide layer, on first phase, high resistance, titanium disilicide regions. The capping, silicon oxide layer, featuring a compressive stress, reduces the risk of titanium disilicide regions, formed with a tensile stress, from adhesion loss, or peeling, from underlying regions of the MOSFET device, such as from the top surface of a narrow width, polysilicon gate structure. In addition the capping silicon oxide layer protects underlying titanium disilicide regions from the ambient used during the anneal cycle used to convert the first phase, high resistance, titanium disilicide region, to the second phase, low resistance, titanium disilicide region.
摘要翻译：已经开发了在MOSFET器件的区域上形成低电阻二硅化钛层的工艺。该方法的特征在于在第一相，高电阻，二硅化钛区域上沉积封盖的氧化硅层。封装，氧化硅层具有压缩应力，降低了形成有拉伸应力的二硅化钛区域从MOSFET器件的下面区域的粘附损失或剥离的风险，例如从狭窄的顶部表面宽度，多晶硅栅结构。此外，封盖氧化硅层保护下游的二硅化钛区域与用于将第一相，高电阻，二硅化钛区域转化为第二相，低电阻，二硅化钛区域的退火循环期间使用的环境。

10. 发明授权

US6156629A Method for patterning a polysilicon gate in deep submicron technology 有权
标题翻译：在深亚微米技术中构图多晶硅栅极的方法
公开(公告)号：US6156629A
公开(公告)日：2000-12-05
申请号：US164998
申请日：1998-10-01
申请人： Hun-Jan Tao , Yuan-Chang Huang
发明人： Hun-Jan Tao , Yuan-Chang Huang
IPC分类号： H01L21/28 , H01L21/311 , H01L21/3213 , H01L21/26
CPC分类号： H01L21/28123 , H01L21/31116 , H01L21/31138 , H01L21/32137 , Y10S438/952
摘要： A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer and the hard mask layer by flowing fluorocarbon gas species gas and argon gas, and applying a first TCP Power and a first Bias power;b) in STEP 2, stripping the bottom anti-reflective coating (BARC) layer by flowing a oxygen; and applying a second TCP Power and second Bias power;c) Placing the substrate into a polysilicon high density plasma etcher and performing the following step: in STEP 3--etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a third TCP Power and a third Bias power.
摘要翻译：使用三步蚀刻工艺使用氧化物硬掩模蚀刻多晶硅的方法。第一步和第二步在高密度等离子体（例如，TCP-变压耦合等离子体）氧化物蚀刻器中进行。步骤3，多晶硅蚀刻在不同的蚀刻器（例如，多RIE蚀刻器）中进行。形成多层半导体结构35（图1），包括：基板10，栅极氧化物层14，多晶硅层18，硬掩模层22和底部抗反射涂层（BARC）层26和抗蚀剂层30. a）在步骤1中，通过流过碳氟化合物气体种类的气体和氩气蚀刻底部抗反射涂层（BARC）层和硬掩模层，并施加第一TCP电力和第一偏压功率; b）在步骤2中，通过流动氧来汽提底部抗反射涂层（BARC）层; 以及施加第二TCP功率和第二偏置功率; c）将衬底放入多晶硅高密度等离子体蚀刻机中，并执行以下步骤：在步骤3中，通过流动氯物质，氧物种蚀刻多晶硅层; 氦物种和溴气物种，并应用第三个TCP电源和第三个偏置电源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式