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1. 发明授权

US6157047A Light emitting semiconductor device using nanocrystals 失效
标题翻译：使用纳米晶体的发光半导体器件
公开(公告)号：US6157047A
公开(公告)日：2000-12-05
申请号：US143106
申请日：1998-08-28
申请人： Shinobu Fujita , Atsushi Kurobe
发明人： Shinobu Fujita , Atsushi Kurobe
IPC分类号： H01L29/06 , H01L27/12 , H01L27/15 , H01L29/66 , H01L33/04 , H01L33/16 , H01L33/34 , H01L33/44 , H01L29/00
CPC分类号： H01L33/34 , H01L33/18 , H01L27/15
摘要： A device structure provides improved efficiency of light emission from a light emitting element made of silicon while rendering such emission electrically controllable. Silicon in the light emitting element comprises fine microcrystals, which are miniaturized sufficiently to cause a quantum size effect. The microcrystals may be 10 nanometers (nm) or less in grain size. A dielectric film of 5 nm thick or less is formed containing therein such microcrystals. The microcrystal structure section is disposed between p- and n-type semiconductor layers. These layers are brought into electrical contact with the microcrystal structure only, while causing the remaining portions to be electrically insulative by a dielectric film or the like. Elementary particles of the opposite polarities, e.g. electrons and holes, are injected by tunnel effect into the microcrystals resulting in emission of light rays with increased efficiency.
摘要翻译：器件结构提供了由硅制成的发光元件提供的发光效率，同时使这种发射电可控制。发光元件中的硅包括细小的微晶，其小型化以产生量子尺寸效应。微晶体的粒径可以为10纳米（nm）以下。形成5nm以下的电介质膜，其中含有这样的微晶。微晶结构部分设置在p型和n型半导体层之间。这些层仅与微结晶结构电接触，同时通过介电膜等使剩余部分电绝缘。具有相反极性的基本粒子，例如电子和空穴通过隧道效应注入到微晶中，导致光线的发射效率提高。

2. 发明授权

US06369438B1 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06369438B1
公开(公告)日：2002-04-09
申请号：US09468923
申请日：1999-12-22
申请人： Naoharu Sugiyama , Atsushi Kurobe
发明人： Naoharu Sugiyama , Atsushi Kurobe
IPC分类号： H01L31117
CPC分类号： H01L21/7624 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02576 , H01L21/0262 , H01L29/1054 , H01L29/157 , H01L29/7842 , H01L31/028
摘要： A method of manufacturing a semiconductor device comprising the steps of forming a first crystal silicon layer doped with oxygen on a single crystal silicon substrate, forming a crystal silicon-germanium layer on the first crystal silicon layer, forming a second crystal silicon layer on the crystal silicon-germanium layer, and imparting strain to the second crystal silicon layer by a thermal treatment.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在单晶硅衬底上形成掺杂有氧的第一晶体硅层，在第一晶体硅层上形成晶体硅 - 锗层，在晶体上形成第二晶体硅层硅锗层，并通过热处理赋予第二晶体硅层的应变。

3. 发明授权

US6060743A Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same 失效
标题翻译：具有多层IV族纳米晶体量子点浮栅的半导体存储器件及其制造方法
公开(公告)号：US6060743A
公开(公告)日：2000-05-09
申请号：US82613
申请日：1998-05-20
申请人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
发明人： Naoharu Sugiyama , Tsutomu Tezuka , Riichi Katoh , Atsushi Kurobe , Tetsufumi Tanamoto
IPC分类号： H01L29/788 , H01L21/336 , H01L29/06 , H01L29/15
CPC分类号： B82Y10/00 , H01L29/7883 , H01L29/7888 , Y10S438/962
摘要： The semiconductor device comprises a first insulating layer formed on the semiconductor substrate, at least one double-deck semiconductor nanocrystal formed on the first insulating layer, the at least one double-deck semiconductor nanocrystal comprising a first semiconductor nanocrystal and a second semiconductor nanocrystal stacked one upon the other via a second insulating layer, and a third insulating layer selectively formed on the first insulating layer so as to cover the at least one double-deck semiconductor nanocrystal.
摘要翻译：所述半导体器件包括形成在所述半导体衬底上的第一绝缘层，形成在所述第一绝缘层上的至少一个双层半导体纳米晶体，所述至少一个双层半导体纳米晶体包括第一半导体纳米晶体和第二半导体纳米晶体，另一方面通过第二绝缘层，以及选择性地形成在第一绝缘层上以覆盖至少一个双层半导体纳米晶体的第三绝缘层。

4. 发明授权

US5253262A Semiconductor laser device with multi-directional reflector arranged therein 失效
标题翻译：其中布置有多向反射器的半导体激光器件
公开(公告)号：US5253262A
公开(公告)日：1993-10-12
申请号：US784711
申请日：1991-10-30
申请人： Atsushi Kurobe , Tsutomu Tezuka , Tetsuo Sadamasa , Mitsuhiro Kushibe , Yoshito Kawakyu
发明人： Atsushi Kurobe , Tsutomu Tezuka , Tetsuo Sadamasa , Mitsuhiro Kushibe , Yoshito Kawakyu
IPC分类号： H01S5/10 , H01S5/12 , H01S5/183 , H01S5/20 , H01S5/22 , H01S5/227 , H01S5/323 , H01S5/40 , H01S3/19
CPC分类号： H01S5/18327 , B82Y20/00 , H01S5/18388 , H01S5/227 , H01S2301/18 , H01S5/1042 , H01S5/1071 , H01S5/1078 , H01S5/1082 , H01S5/1228 , H01S5/18305 , H01S5/18308 , H01S5/18319 , H01S5/1835 , H01S5/18352 , H01S5/2004 , H01S5/2027 , H01S5/2205 , H01S5/2275 , H01S5/32308 , H01S5/34313 , H01S5/4056
摘要： A microcavity semiconductor laser disclosed therein includes a double-heterostructure section including an intermediate active layer sandwiched between a first or lower cladding layer and a second or upper cladding layer above a semiconductive substrate. A first multi-layered reflector section is arranged between the substrate and the double-heterostructure section to have its reflectance which becomes maximum near the oscillation wavelength of the laser. The upper cladding layer is semi-spherically formed. A three-dimensional optical reflector covers the double-heterostructure section, for controlling spontaneous emission obtained in the double-heterostructure section along various directions, and for increasing the coupling ratio of spontaneous emission with a specific laser mode, thereby to decrease the threshold current.
摘要翻译：其中公开的微腔半导体激光器包括双异质结构部分，其包括夹在第一或下包层之间的中间有源层和半导体衬底之上的第二或上覆层。第一多层反射器部分布置在基板和双异质结构部分之间，使其反射率在激光器的振荡波长附近变得最大。上覆层是半球形的。三维光反射器覆盖双异质结构部分，用于控制沿着各个方向的双异质结构部分中获得的自发辐射，并且用于增加具有特定激光模式的自发发射的耦合比，从而降低阈值电流。

5. 发明授权

US4810670A Method of manufacturing an embedded type semiconductor laser 失效
标题翻译：嵌入式半导体激光器的制造方法
公开(公告)号：US4810670A
公开(公告)日：1989-03-07
申请号：US943760
申请日：1986-12-19
申请人： Hideto Furuyama , Atsushi Kurobe
发明人： Hideto Furuyama , Atsushi Kurobe
IPC分类号： H01L21/308 , H01L21/306 , H01S5/00 , H01S5/06 , H01S5/20 , H01S5/34 , H01L21/203
CPC分类号： B82Y20/00 , H01L33/0062 , H01S5/34 , H01S5/2059
摘要： In an embedded type semiconductor laser, at least three layers of a first conduction type clad layer, a quantum well active layer which contains a first or second conduction type or a pn junction, and a second conduction type clad layer, are grown successively on a first conduction type substrate. A high concentration impurity doped layer is provided excluding a predetermined striped region, situated adjacent to the active layer. An impurity diffusion is carried out by heat treatment which diffuses dopant from the high concentration impurity doped layer to the active layer.
摘要翻译：在嵌入式半导体激光器中，在第一导电型覆盖层，含有第一导电型或第二导电型或pn结的量子阱有源层和第二导电型覆盖层中至少3层，第一导电型衬底。除了与有源层相邻的预定条纹区域之外，提供高浓度杂质掺杂层。通过将掺杂剂从高浓度杂质掺杂层扩散到活性层的热处理进行杂质扩散。

6. 发明授权

US4701774A Light emitting semiconductor device 失效
标题翻译：发光半导体器件
公开(公告)号：US4701774A
公开(公告)日：1987-10-20
申请号：US810093
申请日：1985-12-18
申请人： Paul W. A. McIlroy , Atsushi Kurobe , Hideto Furuyama
发明人： Paul W. A. McIlroy , Atsushi Kurobe , Hideto Furuyama
IPC分类号： H01L33/06 , H01L33/14 , H01L33/30 , H01S5/00 , H01S5/30 , H01S5/34 , H01S5/343 , H01L33/00
CPC分类号： H01L33/06 , B82Y20/00 , H01S5/34 , H01S5/305 , H01S5/3432
摘要： In a carrier injection type light emitting semiconductor device with a QW structure, a p-type impurity doped layer and/or an n-type impurity doped layer are inserted into an optical wave guide layer so as to cancel an internal electric field in an active region.
摘要翻译：在具有QW结构的载流子注入型发光半导体器件中，将p型杂质掺杂层和/或n型杂质掺杂层插入到光波导层中，以消除活性物质中的内部电场地区。

7. 发明授权

US06917096B2 Semiconductor device and method of manufacturing substrate 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US06917096B2
公开(公告)日：2005-07-12
申请号：US10611157
申请日：2003-07-02
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L21/205 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/84 , H01L29/10 , H01L29/51 , H01L29/78 , H01L29/786 , H01L31/117
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

8. 发明授权

US06607948B1 Method of manufacturing a substrate using an SiGe layer 有权
标题翻译：使用SiGe层制造衬底的方法
公开(公告)号：US06607948B1
公开(公告)日：2003-08-19
申请号：US09935685
申请日：2001-08-24
申请人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
发明人： Naoharu Sugiyama , Atsushi Kurobe , Tsutomu Tezuka , Tomohisa Mizuno , Shinichi Takagi
IPC分类号： H01L2184
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02502 , H01L21/02532 , H01L21/02664 , H01L21/28255 , H01L21/31675 , H01L29/165 , H01L29/513 , H01L29/517 , H01L29/66477 , H01L29/66666 , H01L29/66742 , H01L29/7827 , H01L29/7833 , H01L29/7848 , H01L29/78687 , Y10S438/938
摘要： A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.
摘要翻译：半导体器件包括基底，形成在基底基底上的氧化硅层，形成在氧化硅层上的第一半导体层，第一半导体层包括Ge浓度不小于30原子％的SiGe层，第二半导体层形成在所述第一半导体层上的所述半导体层，所述第二半导体层包括Ge层或Ge浓度高于所述第一半导体层的SiGe层;栅电极，其被配置为在所述第二半导体层的表面区域中引入沟道，以及形成在所述第二半导体层和所述栅电极之间的栅极绝缘膜。

9. 发明授权

US5847419A Si-SiGe semiconductor device and method of fabricating the same 失效
标题翻译： Si-SiGe半导体器件及其制造方法
公开(公告)号：US5847419A
公开(公告)日：1998-12-08
申请号：US931411
申请日：1997-09-16
申请人： Seiji Imai , Yoshiko Hiraoka , Atsushi Kurobe , Naoharu Sugiyama , Tsutomu Tezuka
发明人： Seiji Imai , Yoshiko Hiraoka , Atsushi Kurobe , Naoharu Sugiyama , Tsutomu Tezuka
IPC分类号： H01L27/06 , H01L27/092 , H01L29/786 , H01L29/161
CPC分类号： H01L29/78654 , H01L27/0605 , H01L27/0688 , H01L27/0922
摘要： A semiconductor device comprises a semiconductor substrate, a first semiconductor layer under compressive strain formed on the semiconductor substrate, a p-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in a predetermined region of the first semiconductor layer, a second semiconductor layer in a lattice-relaxation condition formed on the first semiconductor layer in a region other than the predetermined region with an insulating film lying therebetween, wherein the insulating film has an opening and the first and second semiconductor layers are connected through the opening, a third semiconductor layer under tensile strain formed on the second semiconductor layer, and an n-type MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed in the third semiconductor layer.
摘要翻译：半导体器件包括半导体衬底，形成在半导体衬底上的压缩应变下的第一半导体层，形成在第一半导体层的预定区域中的p型MISFET（金属绝缘体半导体场效应晶体管），第二半导体层形成在第一半导体层上的除了预定区域之外的区域中的绝缘膜的晶格弛豫状态，其中绝缘膜具有开口，并且第一和第二半导体层通过开口连接，第三半导体层在第二半导体层上形成的拉伸应变下，形成在第三半导体层中的n型MISFET（金属绝缘子半导体场效应晶体管）。

10. 发明授权

US5304514A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5304514A
公开(公告)日：1994-04-19
申请号：US687569
申请日：1991-04-19
申请人： Tohru Nishibe , Shinya Nunoue , Atsushi Kurobe
发明人： Tohru Nishibe , Shinya Nunoue , Atsushi Kurobe
IPC分类号： H01L21/306 , H01L21/00 , H01L21/02 , H01L21/302 , H01L21/463
CPC分类号： H01L21/30621
摘要： The present invention provides a dry etching method, having the steps of introducing a mixed gas consisting of a reactive gas and an inert gas into a plasma chamber for generating a plasma, with the partial pressure of each of these gas components being controlled, exciting the mixed gas within the plasma chamber so as to generate ionized particles and excited particles having high reactivity, withdrawing the particles generated in the plasma chamber into a sample chamber having a compound semiconductor substrate housed therein, and physically and chemically etching the compound semiconductor substrate with the particles.
摘要翻译：本发明提供一种干式蚀刻方法，其具有以下步骤：将由反应性气体和惰性气体组成的混合气体引入用于产生等离子体的等离子体室中，这些气体组分中的每一个的分压被控制，激发在等离子体室内混合气体，以产生电离粒子和具有高反应性的激发粒子，将等离子体室中产生的粒子排出到容纳化合物半导体衬底的样品室中，并用化学半导体衬底物理和化学蚀刻化合物半导体衬底粒子。

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