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1. 发明授权

US5270232A Process for fabricating field effect transistor 失效
标题翻译：制造场效应晶体管的工艺
公开(公告)号：US5270232A
公开(公告)日：1993-12-14
申请号：US943018
申请日：1992-09-10
申请人： Shinichiro Kimura , Shoji Shukuri , Hiromasa Noda , Digh Hisamoto , Hideyuki Matsuoka , Kazuyoshi Torii , Natsuki Yokoyama , Toshiyuki Yoshimura , Kazunori Tsujimoto , Eiji Takeda
发明人： Shinichiro Kimura , Shoji Shukuri , Hiromasa Noda , Digh Hisamoto , Hideyuki Matsuoka , Kazuyoshi Torii , Natsuki Yokoyama , Toshiyuki Yoshimura , Kazunori Tsujimoto , Eiji Takeda
IPC分类号： H01L29/78 , H01L21/285 , H01L21/336 , H01L21/70
CPC分类号： H01L29/66606 , H01L21/28525 , H01L29/66621 , Y10S438/947
摘要： A very thin oxide film is formed at an opening formed in an insulator film and a conductor layer, on a substrate, and impurity-containing polysilicon is formed on the sidewall of the opening. Impurity diffusion from the from the silicon into the substrate through the very thin oxide film causes a lowering in effective concentration of the diffused impurities, resulting in the formation of shallower source/drain region. Thereafter, a gate insulator film and a gate electrode are formed on the substrate surface in an area bounded by an insulator film formed on the sidewall of the opening. The gate electrode smaller than the opening, the size of which corresponds to the limit of processing, and the shallower source/drain region afford a miniaturized MOSFET.
摘要翻译：在基板上形成绝缘体膜和导体层的开口处形成非常薄的氧化膜，并且在开口的侧壁上形成含杂质的多晶硅。通过非常薄的氧化膜从硅到衬底的杂质扩散导致扩散杂质的有效浓度降低，导致形成较浅的源/漏区。此后，在由形成在开口的侧壁上的绝缘膜限定的区域中的基板表面上形成栅绝缘膜和栅电极。小于开口的栅极电极，其尺寸对应于处理极限，并且较浅的源极/漏极区域提供小型化的MOSFET。

2. 发明授权

US08052495B2 Method for producing spark plug by projection welding and spark plug thereof 有权
标题翻译：通过突起焊接和火花塞生产火花塞的方法
公开(公告)号：US08052495B2
公开(公告)日：2011-11-08
申请号：US12057242
申请日：2008-03-27
申请人： Tomoaki Kato , Kazuyoshi Torii , Mamoru Musasa
发明人： Tomoaki Kato , Kazuyoshi Torii , Mamoru Musasa
IPC分类号： H01T21/02
CPC分类号： H01T13/32 , H01T21/02
摘要： A spark plug (100) including a center electrode (130) and a ground electrode (140), which is formed by joining a ground electrode chip (143) to a ground electrode base material (141) via an intermediate member (142). A method for producing the spark plug (100) includes providing a projecting portion (142p) on the intermediate member (142), and projection-welding the intermediate member (142) to the ground electrode base material (141) by means of the projecting portion (142p), to thereby join the intermediate member 142 to the ground electrode base material (141). Further, the intermediate member (142) of the spark plug (100) includes a cylindrical columnar portion (142e) which is joined to the ground electrode chip (143), and a flange portion (142d) which is joined to the ground electrode base material (141) and which flange portion (142d) has a diameter greater than that of the cylindrical columnar portion (142e).
摘要翻译：一种火花塞（100），包括通过中间构件（142）将接地电极芯片（143）接合到接地电极基材（141）而形成的中心电极（130）和接地电极（140）。一种火花塞（100）的制造方法，其特征在于，在所述中间部件（142）上设置突出部（142p），通过所述突出部（142）将所述中间部件（142）投射到所述接地电极母材（142p），从而将中间构件142接合到接地电极基材（141）。此外，火花塞（100）的中间部件（142）包括与接地电极芯片（143）接合的圆筒状的柱状部（142e）和与接地电极基体接合的凸缘部（142d）材料（141），并且所述凸缘部分（142d）的直径大于圆柱形柱状部分（142e）的直径。

3. 发明授权

US08044562B2 Spark plug 有权
标题翻译：火花塞
公开(公告)号：US08044562B2
公开(公告)日：2011-10-25
申请号：US12741764
申请日：2008-11-12
申请人： Mamoru Musasa , Naomichi Miyashita , Kazuyoshi Torii
发明人： Mamoru Musasa , Naomichi Miyashita , Kazuyoshi Torii
IPC分类号： H01T13/20
CPC分类号： H01T13/39
摘要： There is provided a spark section (80) of needle-like shape protruding from an inner surface (33) of a ground electrode (30) to define a spark gap between the spark section and an electrode tip on a center electrode. The spark section (80) has a noble metal member (81) and an intermediate member (86) joined to each other. The materials of the noble metal member (81) and the intermediate member (86) are selected in such a manner that the thermal conductivity of the intermediate member (86) is lower than that of the noble metal member (81). This limits heat radiation through the heat radiation passage from the noble metal member (81) through the intermediate member (86) to the ground electrode (30) so as to maintain the noble metal member (81) at a higher temperature than conventional types and reduce a quenching effect of the noble metal member (81) on a flame core generated in the spark gap for improvement in ignition performance.
摘要翻译：设置从接地电极（30）的内表面（33）突出的针状的火花部（80），以在火花部和中心电极上的电极尖之间限定火花隙。火花部（80）具有彼此接合的贵金属部件（81）和中间部件（86）。选择贵金属构件（81）和中间构件（86）的材料，使得中间构件（86）的导热率低于贵金属构件（81）的导热率。这就限制了通过从贵金属构件（81）穿过中间构件（86）到接地电极（30）的散热通道的热辐射，以便将贵金属构件（81）保持在比常规类型更高的温度降低贵金属构件（81）对火花隙中产生的火焰核心的淬火效果，以提高点火性能。

4. 发明申请

US20080238282A1 METHOD FOR PRODUCING SPARK PLUG AND SPARK PLUG 有权
标题翻译：生产火花塞和火花塞的方法
公开(公告)号：US20080238282A1
公开(公告)日：2008-10-02
申请号：US12057242
申请日：2008-03-27
申请人： Tomoaki Kato , Kazuyoshi Torii , Mamoru Musasa
发明人： Tomoaki Kato , Kazuyoshi Torii , Mamoru Musasa
IPC分类号： H01T13/20
CPC分类号： H01T13/32 , H01T21/02
摘要： A spark plug (100) including a center electrode (130) and a ground electrode (140), which is formed by joining a ground electrode chip (143) to a ground electrode base material (141) via an intermediate member (142). A method for producing the spark plug (100) includes providing a projecting portion (142p) on the intermediate member (142), and projection-welding the intermediate member (142) to the ground electrode base material (141) by means of the projecting portion (142p), to thereby join the intermediate member 142 to the ground electrode base material (141). Further, the intermediate member (142) of the spark plug (100) includes a cylindrical columnar portion (142e) which is joined to the ground electrode chip (143), and a flange portion (142d) which is joined to the ground electrode base material (141) and which flange portion (142d) has a diameter greater than that of the cylindrical columnar portion (142e).
摘要翻译：一种火花塞（100），包括通过中间构件（142）将接地电极芯片（143）接合到接地电极基材（141）而形成的中心电极（130）和接地电极（140）。一种火花塞（100）的制造方法，其特征在于，在所述中间部件（142）上设置突出部（142p），通过所述中间部件（142）将所述中间部件（142）投射到所述接地电极母材突起部分（142p），从而将中间构件142接合到接地电极基材（141）。此外，火花塞（100）的中间构件（142）包括接合到接地电极芯片（143）的圆柱形柱状部分（142e）和接合到地面的凸缘部分（142d）电极基体材料（141），并且所述凸缘部分（142d）的直径大于圆柱形部分（142e）的直径。

5. 发明申请

US20060276097A1 Spark plug manufacturing method 有权
标题翻译：火花塞制造方法
公开(公告)号：US20060276097A1
公开(公告)日：2006-12-07
申请号：US10565902
申请日：2004-11-18
申请人： Akira Suzuki , Tomoaki Kato , Kazuyoshi Torii , Akikazu Taido
发明人： Akira Suzuki , Tomoaki Kato , Kazuyoshi Torii , Akikazu Taido
IPC分类号： H01T13/20
CPC分类号： H01T21/02 , H01T13/20 , H01T13/39
摘要： There is provided a method for producing a spark plug in which welding strength between a noble metal tip and an electrode joined by laser welding can be restrained from becoming weak. A noble metal tip (90) to be joined to a center electrode (2) or ground electrode of a spark plug to form a spark discharge gap is resistance-welded to each electrode containing no noble metal and then laser-welded. In the noble metal tip (90) exposed under a severe environment involving spark discharge, a molten portion (80) formed in such a manner that a portion of the noble metal tip (90) and a portion of the electrode are melted by laser welding and a non-molten portion (95) on the noble metal tip (90) side are apt to be peeled from each other in a boundary surface (83) between the molten portion (80) and the non-molten portion (95). The noble metal content in the molten portion (80) however becomes higher because a flange portion is formed in a bottom portion by pressing force applied on the noble metal tip (90) at the time of resistance welding and then irradiated with a laser beam. Accordingly, peeling can be prevented from occurring in the boundary surface (83).
摘要翻译：提供一种用于制造火花塞的方法，其中可以抑制贵金属电极头和通过激光焊接接合的电极之间的焊接强度变弱。要连接到火花塞的中心电极（2）或接地电极以形成火花放电间隙的贵金属端头（90）被电阻焊接到不含贵金属的每个电极上，然后被激光焊接。在涉及火花放电的恶劣环境下露出的贵金属电极头（90）中，以使得贵金属电极头（90）的一部分和电极的一部分通过激光焊接而熔化的方式形成的熔融部（80）并且在熔融部分（80）和非熔融部分（95）之间的边界表面（83）中，在贵金属端头（90）侧上的非熔融部分（95）易于彼此剥离。然而，熔融部分（80）中的贵金属含量变高，因为通过在电阻焊接时施加在贵金属电极头（90）上的压力而在底部形成凸缘部分，然后用激光束照射。因此，能够防止在边界面（83）发生剥离。

6. 发明授权

US07042055B2 Semiconductor device and manufacturing thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US07042055B2
公开(公告)日：2006-05-09
申请号：US10174948
申请日：2002-06-20
申请人： Shinichi Saito , Kazuyoshi Torii , Takahiro Onai , Toshiyuki Mine
发明人： Shinichi Saito , Kazuyoshi Torii , Takahiro Onai , Toshiyuki Mine
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62
CPC分类号： H01L29/4983 , H01L21/28017 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L29/4916 , H01L29/4925 , H01L29/513 , H01L29/517 , H01L29/66545
摘要： In a miniaturized field effect transistor, the roughness of the interface between a gate dielectric film and a gate electrode is controlled on an atomic scale. The thickness variation of the gate dielectric film is lowered, whereby a field effect transistor with high mobility is manufactured. An increase in the mobility in the field effect transistor can be achieved not only in the case of using a conventional SiO2 thermal oxide film as the gate dielectric film but also in the case of using a high dielectric material for the gate dielectric film.
摘要翻译：在小型场效应晶体管中，栅介质膜与栅电极之间的界面的粗糙度被控制在原子尺度上。栅电介质膜的厚度变化降低，由此制造具有高迁移率的场效应晶体管。场效应晶体管的迁移率的增加不仅可以在使用常规的SiO 2热氧化膜作为栅极电介质膜的情况下实现，而且在使用高介电材料的情况下也可以实现用于栅介质膜。

7. 发明授权

US06894334B2 Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US06894334B2
公开(公告)日：2005-05-17
申请号：US10376329
申请日：2003-03-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

8. 发明申请

US20050045970A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050045970A1
公开(公告)日：2005-03-03
申请号：US10913551
申请日：2004-08-09
申请人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
发明人： Tsunetoshi Arikado , Takaaki Kawahara , Kazuyoshi Torii , Hiroshi Kitajima , Seiichi Miyazaki
IPC分类号： C23C16/42 , H01L21/28 , H01L21/316 , H01L21/336 , H01L29/51 , H01L29/78 , H01L29/76
CPC分类号： H01L21/28185 , H01L21/28194 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
摘要翻译：硅衬底上的栅极绝缘膜包括SiO 2膜和高k膜。高k膜包含过渡金属，铝，硅和氧。高k膜中的硅的浓度高于与SiO 2膜的界面附近和与栅电极的界面附近的过渡金属和铝的浓度。此外，优选的是，至少在与SiO 2膜的界面附近或与栅电极的界面附近的硅中的浓度最高，随着与这些界面的距离而逐渐减小，并且变得最低在高k电影的中心部分。

9. 发明授权

US06787451B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06787451B2
公开(公告)日：2004-09-07
申请号：US10216792
申请日：2002-08-13
申请人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
发明人： Yasuhiro Shimamoto , Katsunori Obata , Kazuyoshi Torii , Masahiko Hiratani
IPC分类号： H01L2972
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02178 , H01L21/02266 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/28061 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/3141 , H01L21/3143 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L21/31645 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545
摘要： In a method for manufacturing an FET having a gate insulation film with an SiO2 equivalent thickness of 2 nm or more and capable of suppressing the leak current to {fraction (1/100)} or less compared with existent SiO2 films, an SiO2 film of 0.5 nm or more is formed at a boundary between an Si substrate (polycrystalline silicon gate) and a high dielectric insulation film, and the temperature for forming the SiO2 film is made higher than the source-drain activating heat treatment temperature in the subsequent steps. As such, a shifting threshold voltage by the generation of static charges or lowering of a drain current caused by degradation of mobility can be prevented so as to reduce electric power consumption and increase current in a field effect transistor of a smaller size.
摘要翻译：在具有SiO 2当量厚度为2nm以上的栅极绝缘膜的FET的制造方法中，能够将漏电流抑制到{部分（与现有的SiO 2膜相比为1/100以下）的SiO 2膜为0.5nm 以上的Si基板（多晶硅栅极）和高介电绝缘膜之间的边界处形成，并且使SiO 2膜的形成温度高于后续工序中的源极 - 漏极活化热处理温度，因此可以防止由静电电荷的产生产生的偏移阈值电压或由迁移率降低引起的漏极电流的降低，从而降低较小尺寸的场效应晶体管的电力消耗和增加电流。

10. 发明授权

US06548847B2 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM 失效
标题翻译：具有通过连接孔暴露的第一布线的半导体集成电路器件，连接孔中的过渡金属膜和铝导线之间的过渡金属膜以及铝导线和过渡金属膜之间的过渡金属氮化物膜
公开(公告)号：US06548847B2
公开(公告)日：2003-04-15
申请号：US09899921
申请日：2001-07-09
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： H01L2976
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L24/45 , H01L24/48 , H01L27/0922 , H01L27/0928 , H01L27/10808 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

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