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1. 发明授权

US5898606A Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效
标题翻译：电可编程和可擦除的非易失性半导体存储器件及其操作方法
公开(公告)号：US5898606A
公开(公告)日：1999-04-27
申请号：US841372
申请日：1997-04-30
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
摘要翻译：在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。因此，多个存储单元的阈值电压增加。在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。因此，所选存储单元的阈值电压降低。

2. 发明授权

US5659505A Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效
标题翻译：电可编程和可擦除的非易失性半导体存储器件及其操作方法
公开(公告)号：US5659505A
公开(公告)日：1997-08-19
申请号：US509250
申请日：1995-07-31
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C11/40
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.
摘要翻译：在擦除时，电子同时从多个存储单元的源中注入到浮动栅极中。因此，多个存储单元的阈值电压增加。在编程中，电子从所选择的存储单元的浮动栅极发射到漏极。因此，所选存储单元的阈值电压降低。

3. 发明授权

US5745417A Electrically programmable and erasable nonvolatile semiconductor memory device and operating method therefor 失效
公开(公告)号：US5745417A
公开(公告)日：1998-04-28
申请号：US661930
申请日：1996-06-11
申请人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
发明人： Shinichi Kobayashi , Yasushi Terada , Yoshikazu Miyawaki , Takeshi Nakayama , Tomoshi Futatsuya , Natsuo Ajika , Yuichi Kunori , Hiroshi Onoda , Atsushi Fukumoto , Makoto Ohi
IPC分类号： G11C16/04 , G11C16/16 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , G11C7/00
CPC分类号： H01L27/11517 , G11C16/0408 , G11C16/0416 , G11C16/16 , H01L27/105 , H01L27/115 , H01L27/11546 , H01L29/7883
摘要： In erasing, electrons are simultaneously injected into floating gates from sources of a plurality of memory cells. Thus, the threshold voltages of the plurality of memory cells are increased. In programming, electrons are emitted from a floating gate of a selected memory cell to a drain. Thus, the threshold voltage of the selected memory cell is reduced.

4. 发明授权

US5338957A Nonvolatile semiconductor device and a method of manufacturing thereof 失效
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US5338957A
公开(公告)日：1994-08-16
申请号：US110151
申请日：1993-08-23
申请人： Atsushi Fukumoto , Makoto Ohi , Hiroshi Onoda , Natsuo Ajika , Yuichi Kunori
发明人： Atsushi Fukumoto , Makoto Ohi , Hiroshi Onoda , Natsuo Ajika , Yuichi Kunori
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68 , G11C11/34
CPC分类号： H01L27/115
摘要： The width of a charge storage electrode and a control electrode in the column direction is set to be wider above an element isolation region than that above a channel region. Therefore, the capacitance between the control electrode and the charge storage electrode can be increased to improve the coupling ratio in a nonvolatile semiconductor memory device. Also, a first interconnection layer is equal in height above the control electrode and above the channel region, so that patterning of the first interconnection layer can be carried out easily and precisely.
摘要翻译：在列方向上的电荷存储电极和控制电极的宽度被设定为比元件隔离区域高于沟道区域以上的宽度。因此，可以增加控制电极和电荷存储电极之间的电容，以提高非易失性半导体存储器件中的耦合比。此外，第一互连层在控制电极上方高于沟道区域的高度相等，使得可以容易且精确地执行第一互连层的图案化。

5. 发明授权

US5538912A Method of making memory cells with peripheral transistors 失效
标题翻译：制造具有外围晶体管的存储单元的方法
公开(公告)号：US5538912A
公开(公告)日：1996-07-23
申请号：US370755
申请日：1995-01-10
申请人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
发明人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
IPC分类号： H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.
摘要翻译：在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。在导电层，栅电极和控制栅电极上形成层间绝缘膜。在层间绝缘膜的预定位置处形成接触孔。在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

6. 发明授权

US5400278A Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5400278A
公开(公告)日：1995-03-21
申请号：US114229
申请日：1993-09-01
申请人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
发明人： Yuichi Kunori , Natsuo Ajika , Hiroshi Onoda , Makoto Ohi , Atsushi Fukumoto
IPC分类号： H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/112 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/10844 , H01L27/105 , H01L27/11517 , H01L27/11526
摘要： In a semiconductor memory device according to the present invention, a conductive layer is formed on a field oxide film in a boundary region on the main surface of a semiconductor substrate. A floating gate electrode, an interlayer insulating film, and a control gate electrode are formed on the semiconductor substrate in a memory cell array region with a gate insulating film interposed therebetween. A gate electrode is formed in a peripheral circuit region with the gate insulating film interposed therebetween. An interlayer insulating film is formed on the conductive layer, the gate electrode, and the control gate electrode. A contact hole is formed at a predetermined position of the interlayer insulating film. An interconnection layer is selectively formed on the interlayer insulating film including the inner surface of the contact hole. According to the present invention, it is possible to prevent formation of a concave portion on the surface of the field oxide film in the boundary region. It is also possible to protect the memory cell array region from an external noise by forming the conductive layer on the field oxide film in the boundary region and by fixing the potential of the conductive layer.
摘要翻译：在根据本发明的半导体存储器件中，在半导体衬底的主表面上的边界区域中的场氧化物膜上形成导电层。在半导体衬底上形成有一个栅极绝缘膜和一个控制栅电极的存储单元阵列区域中，栅极绝缘膜插在其间。栅极电极形成在外围电路区域中，栅极绝缘膜插入其间。在导电层，栅电极和控制栅电极上形成层间绝缘膜。在层间绝缘膜的预定位置处形成接触孔。在包括接触孔的内表面的层间绝缘膜上选择性地形成布线层。根据本发明，可以防止在边界区域的场氧化膜的表面上形成凹部。也可以通过在边界区域的场氧化膜上形成导电层，并通过固定导电层的电位来保护存储单元阵列区域免受外部噪声的影响。

7. 发明授权

US08339850B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08339850B2
公开(公告)日：2012-12-25
申请号：US12766624
申请日：2010-04-23
申请人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
发明人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C5/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

8. 发明申请

US20100290292A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100290292A1
公开(公告)日：2010-11-18
申请号：US12766624
申请日：2010-04-23
申请人： Hiroaki TANIZAKI , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
发明人： Hiroaki TANIZAKI , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

9. 发明授权

US07638411B2 Semiconductor wafer, semiconductor chip and dicing method of a semiconductor wafer 有权
标题翻译：半导体晶片，半导体芯片和半导体晶片的切割方法
公开(公告)号：US07638411B2
公开(公告)日：2009-12-29
申请号：US12219646
申请日：2008-07-25
申请人： Ryu Makabe , Yuichi Kunori
发明人： Ryu Makabe , Yuichi Kunori
IPC分类号： H01L21/46
CPC分类号： H01L22/32 , H01L21/78 , H01L2224/48091 , H01L2924/1305 , H01L2924/00014 , H01L2924/00
摘要： The metal wirings of the uppermost layer are exposed so as to be contactable to the probe and arranged so as to be spatially separated from one another via spaces that are approximately parallel to the longitudinal direction of the dicing area, and the position and size of the space is designed considering a thickness of a cutting edge of a blade and relative positioning error, and the blade does not cross any metal wirings when the blade passes through the dicing area, thereby preventing the generation of an abruption or a burr due to the dicing to enhance a yield in IC production.
摘要翻译：最上层的金属布线被暴露以便能够与探针接触并且布置成通过与切割区域的纵向近似平行的空间彼此空间上分开，并且其位置和尺寸考虑到刀片的切割刃的厚度和相对定位误差来设计空间，并且当刀片通过切割区域时刀片不会穿过任何金属布线，从而防止由于切割而产生剥离或毛刺提高IC生产的收益。

10. 发明授权

US07248500B2 Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array 有权
标题翻译：非易失性半导体存储器件具有降低源极电阻对阵列中位置的依赖性
公开(公告)号：US07248500B2
公开(公告)日：2007-07-24
申请号：US11329036
申请日：2006-01-11
申请人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
发明人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
IPC分类号： G11C16/28
CPC分类号： G11C16/26
摘要： A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.
摘要翻译：具有低阈值电压的虚拟单元被布置在与存储单元对准的存储单元阵列中。选择与所选存储单元列相邻的具有低阈值电压的虚拟单元，并且所选择的存储单元的源极局部位线通过这样的虚设单元耦合到全局位线。由于源极本地位线在其两端耦合到接地节点，所以可以减小存储器单元的源极电阻，并且存储单元的源极电阻对存储单元阵列内的位置的依赖性也可以是减少这允许减小存储器单元的源电阻对存储单元阵列内的位置和非易失性半导体存储器件中的温度的依赖性。

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