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1. 发明授权

US08339850B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08339850B2
公开(公告)日：2012-12-25
申请号：US12766624
申请日：2010-04-23
申请人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
发明人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C5/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

2. 发明授权

US09450245B2 Negative material for nonaqueous electrolyte secondary battery and nonaqueous electrolyte secondary battery using the negative material 有权
标题翻译：使用负极材料的非水电解质二次电池和非水电解质二次电池的负极材料
公开(公告)号：US09450245B2
公开(公告)日：2016-09-20
申请号：US10297650
申请日：2002-04-09
申请人： Atsuo Omaru , Hiroaki Tanizaki
发明人： Atsuo Omaru , Hiroaki Tanizaki
IPC分类号： H01M4/13 , H01M4/133 , H01M4/1393 , H01M4/40 , H01M4/58 , H01M4/583 , H01M10/0525 , H01M4/36 , H01M4/62 , H01M4/02
CPC分类号： H01M4/364 , H01M4/13 , H01M4/131 , H01M4/133 , H01M4/134 , H01M4/136 , H01M4/1393 , H01M4/1395 , H01M4/362 , H01M4/386 , H01M4/40 , H01M4/405 , H01M4/485 , H01M4/58 , H01M4/583 , H01M4/625 , H01M10/0525 , H01M10/0568 , H01M10/0569 , H01M2004/027 , Y02E60/122
摘要： The present invention relates to a nonaqueous electrolyte secondary battery comprising an anode (3), a cathode (2) and a nonaqueous electrolyte. The anode forming this battery includes composite particles having a carbon material included in a metallic material. As the metallic material, metal capable of electrochemically reacting with lithium in a nonaqueous electrolyte is included.
摘要翻译：本发明涉及包含阳极（3），阴极（2）和非水电解质的非水电解质二次电池。形成该电池的阳极包括具有包含在金属材料中的碳材料的复合颗粒。作为金属材料，包括能够在非水电解质中与锂电化学反应的金属。

3. 发明授权

US07436699B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07436699B2
公开(公告)日：2008-10-14
申请号：US11645610
申请日：2006-12-27
申请人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
发明人： Hiroaki Tanizaki , Takaharu Tsuji , Yasumitsu Murai , Hideto Hidaka
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/5607 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/0078 , G11C2213/31 , G11C2213/79
摘要： Source lines for a spin injection magnetic memory cell are arranged parallel to word lines for executing writing/reading of data multiple bits at a time. In a write operation, a source line potential changes in a predetermined sequence such that the source line commonly connected to a plurality of selected memory cells is set to pass a current only in one direction in each stage of the operation sequence. For the data write sequence, a current is caused to flow through memory cells according to write data sequentially, or the memory cell has a resistance state set to an initial resistance state before writing, and then changed to a state according to the write data Fast writing can be achieved in the magnetic memory without increasing a memory cell layout area.
摘要翻译：自旋注入磁存储单元的源极线与字线平行地布置，用于一次执行数据多位读写。在写入操作中，源极线电位以预定的顺序改变，使得共同连接到多个选择的存储器单元的源极线被设置为仅在操作序列的每个阶段中在一个方向上传递电流。对于数据写入序列，根据写入数据顺序地使电流流过存储器单元，或者存储单元在写入之前具有设置为初始电阻状态的电阻状态，然后根据写入数据快速变为状态可以在磁存储器中实现写入，而不增加存储单元布局区域。

4. 发明申请

US20080094778A1 LITHIUM-ION CAPACITOR 有权
标题翻译：锂离子电容器
公开(公告)号：US20080094778A1
公开(公告)日：2008-04-24
申请号：US11874338
申请日：2007-10-18
申请人： Hiroaki Tanizaki , Nobuo Ando , Yukinori Hatou
发明人： Hiroaki Tanizaki , Nobuo Ando , Yukinori Hatou
IPC分类号： H01G9/145
CPC分类号： H01G11/32 , H01G11/06 , H01G11/24 , H01G11/50 , Y02E60/13 , Y02T10/7022
摘要： The invention provides a negative electrode material for use with a lithium-ion capacitor, which is high in energy density, output density and excellent in durability. When graphite of which an average distance between 002 lattice planes thereof is within a range from 0.335 nm to 0.337 nm is used for an active material of a negative electrode of a lithium-ion capacitor, the energy density of the capacitor is increased. The output characteristic and the cycle durability can be improved when D10, D50 and D90 are set within predetermined ranges.
摘要翻译：本发明提供一种与锂离子电容器一起使用的负极材料，其能量密度高，输出密度高，耐久性优异。对于锂离子电容器的负极的活性物质，当其002个晶面之间的平均距离在0.335nm〜0.337nm的范围内的石墨被使用时，电容器的能量密度增加。当D＆lt; 10＆gt;，D＆lt; 50＆gt;和D＆gt; 90＆lt;＆gt;之间的输出特性和循环耐久性被设定在预定范围内时。

5. 发明申请

US20060233018A1 Non-volatile memory device having toggle cell 有权
标题翻译：具有切换单元的非易失性存储器件
公开(公告)号：US20060233018A1
公开(公告)日：2006-10-19
申请号：US11400529
申请日：2006-04-10
申请人： Hiroaki Tanizaki
发明人： Hiroaki Tanizaki
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1673 , G11C2213/78
摘要： A tunneling magneto-resistance element is arranged on an upper layer side of a digit line. The tunneling magneto-resistance element is electrically coupled to a source/drain region of an access transistor through a strap and a contact hole. A bit line is electrically coupled to the tunneling magneto-resistance element, and arranged on the upper layer side of the tunneling magneto-resistance element. A plurality of tunneling magneto-resistance elements share one access transistor, so that a non-volatile memory device achieving low area penalty and higher integration can be implemented.
摘要翻译：隧道磁阻元件布置在数字线的上层侧。隧道磁阻元件通过带子和接触孔电耦合到存取晶体管的源极/漏极区域。位线电耦合到隧道磁阻元件，并且布置在隧道磁阻元件的上层侧。多个隧道磁阻元件共享一个存取晶体管，从而可以实现实现低面积损耗和更高集成度的非易失性存储器件。

6. 发明授权

US06842366B2 Thin film magnetic memory device executing self-reference type data read 失效
标题翻译：执行自参考型数据读取的薄膜磁存储器件
公开(公告)号：US06842366B2
公开(公告)日：2005-01-11
申请号：US10383570
申请日：2003-03-10
申请人： Hiroaki Tanizaki , Tsukasa Ooishi , Hideto Hidaka
发明人： Hiroaki Tanizaki , Tsukasa Ooishi , Hideto Hidaka
IPC分类号： G11C11/15 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/14
CPC分类号： G11C11/15 , G11C11/1673
摘要： In one data read operation, data read for reading stored data before and after a predetermined data write magnetic field is applied to a selected memory cell, respectively, is executed, and the data read is executed in accordance with comparison of voltage levels corresponding to the data read operations before and after application of the predetermined data write magnetic field. In addition, data read operations before and after the application of a data write magnetic field are executed using read modify write. It is thereby possible to avoid an influence of an offset or the like resulting from manufacturing irregularities in respective circuits forming a data read path, to improve efficiency of the data read operation with accuracy and to execute a high rate data read operation.
摘要翻译：在一个数据读取操作中，执行用于将预定数据写入磁场之前和之后的存储数据读取的数据分别施加到所选择的存储单元，并且根据与数据读取操作在应用预定数据写入磁场之前和之后。另外，数据写入磁场的应用前后的数据读取操作是使用读修改写进行的。从而可以避免在形成数据读取路径的各个电路中由制造不规则引起的偏移等的影响，从而精确地提高数据读取操作的效率并执行高速数据读取操作。

7. 发明授权

US06762953B2 Nonvolatile memory device with sense amplifier securing reading margin 失效
标题翻译：带有读出放大器的非易失性存储器件确保读取余量
公开(公告)号：US06762953B2
公开(公告)日：2004-07-13
申请号：US10455479
申请日：2003-06-06
申请人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
发明人： Hiroaki Tanizaki , Hideto Hidaka , Tsukasa Ooishi
IPC分类号： G11C1100
CPC分类号： G11C7/04 , G11C7/062 , G11C7/14 , G11C11/16 , G11C16/28 , G11C2207/063
摘要： In a sense amplifier, local I/O lines are maintained at a predetermined voltage by transistors. Transistors forming a current mirror supply an operating current according to a passing current which flows through transistors, to sense nodes. Transistors forming a current mirror extract an operating current according to the passing current which flows through transistors, from sense nodes. As a result, a voltage difference is generated in sense nodes in accordance with the operating current difference.
摘要翻译：在读出放大器中，本地I / O线通过晶体管保持在预定电压。形成电流镜的晶体管根据流过晶体管的通过电流来提供工作电流，以感测节点。形成电流镜的晶体管根据从感测节点流过晶体管的通过电流提取工作电流。结果，根据工作电流差在感测节点产生电压差。

8. 发明授权

US06430091B2 Semiconductor memory device having reduced current consumption at internal boosted potential 失效
标题翻译：半导体存储器件在内部升压电位下具有降低的电流消耗
公开(公告)号：US06430091B2
公开(公告)日：2002-08-06
申请号：US09773621
申请日：2001-02-02
申请人： Hiroaki Tanizaki
发明人： Hiroaki Tanizaki
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4074 , G11C11/4094
摘要： In a three-state circuit issuing a shared gate signal, after an N-channel MOS transistor charges a node issuing an output signal OUT to external power supply potential exvdd, the N-channel MOS transistor is turned off, and a P-channel MOS transistor is turned on to charge the node to boosted potential VPP. Thereby, a power consumed at boosted potential VPP can be reduced, and sizes of transistors of a VPP generating circuit can be reduced-. Thereby, a semiconductor memory device having a small chip size can be achieved.
摘要翻译：在发出共享门信号的三态电路中，在N沟道MOS晶体管对发出输出信号OUT的节点对外部电源电位exvdd进行充电之后，N沟道MOS晶体管被截止，P沟道MOS 晶体管导通，对节点充电以提升电位VPP。由此，可以降低在升压电位VPP下消耗的功率，并且可以减小VPP发生电路的晶体管的尺寸。由此，可以实现具有小芯片尺寸的半导体存储器件。

9. 发明授权

US06381167B2 Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof 有权
公开(公告)号：US06381167B2
公开(公告)日：2002-04-30
申请号：US09781238
申请日：2001-02-13
申请人： Tsukasa Ooishi , Hiroaki Tanizaki
发明人： Tsukasa Ooishi , Hiroaki Tanizaki
IPC分类号： G11C506
CPC分类号： G11C29/848 , G11C7/18 , H01L27/10894 , H01L27/10897
摘要： A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

10. 发明申请

US20120075921A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120075921A1
公开(公告)日：2012-03-29
申请号：US13188924
申请日：2011-07-22
申请人： Hiroaki Tanizaki , Yasumitsu Murai , Takaharu Tsuji , Masanori Hayashikoshi
发明人： Hiroaki Tanizaki , Yasumitsu Murai , Takaharu Tsuji , Masanori Hayashikoshi
IPC分类号： G11C11/02
CPC分类号： G11C8/12 , G11C11/1657 , G11C11/1659 , G11C11/1675
摘要： A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.
摘要翻译：提供一种使用能够实现正常写入操作的段写入方法的半导体器件。第一DL驱动器和第二DL驱动器各自引起磁化电流流过所选块的数字线。 BL驱动器使写入电流在与所选择的段中的所有位线对应的数据信号逻辑的方向上流动，并将数据信号写入所选择的块的存储单元。段解码器当从外部输入一个段的地址时，选择与该地址相对应的一个段，并将其与所选择的第一DL驱动器相连，并且当两个或多个段的地址已被从外部输入，选择对应于地址的两个或更多个段，并将所选择的两个或多个段分别耦合到第一DL驱动器和第二DL驱动器。

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