专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07952926B2 Nonvolatile semiconductor memory device having assist gate 有权
标题翻译：具有辅助门的非易失性半导体存储器件
公开(公告)号：US07952926B2
公开(公告)日：2011-05-31
申请号：US12705357
申请日：2010-02-12
申请人： Takashi Kono , Yuichi Kunori , Hironori Iga
发明人： Takashi Kono , Yuichi Kunori , Hironori Iga
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/0433 , G11C16/24 , G11C16/26
摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
摘要翻译：在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

2. 发明申请

US20100290292A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20100290292A1
公开(公告)日：2010-11-18
申请号：US12766624
申请日：2010-04-23
申请人： Hiroaki TANIZAKI , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
发明人： Hiroaki TANIZAKI , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

3. 发明授权

US07692966B2 Nonvolatile semiconductor memory device having assist gate 有权
标题翻译：具有辅助门的非易失性半导体存储器件
公开(公告)号：US07692966B2
公开(公告)日：2010-04-06
申请号：US12153927
申请日：2008-05-28
申请人： Takashi Kono , Yuichi Kunori , Hironori Iga
发明人： Takashi Kono , Yuichi Kunori , Hironori Iga
IPC分类号： G11C11/34 , G11C8/00
CPC分类号： G11C16/0491 , G11C16/0433 , G11C16/24 , G11C16/26
摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
摘要翻译：在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

4. 发明授权

US07685357B2 Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing 失效
标题翻译：可实现高速数据读取和高速数据写入的多级存储非易失性半导体存储器件
公开(公告)号：US07685357B2
公开(公告)日：2010-03-23
申请号：US12243309
申请日：2008-10-01
申请人： Yuichi Kunori
发明人： Yuichi Kunori
IPC分类号： G06F12/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642
摘要： A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.
摘要翻译：非易失性半导体存储器件每j位（例如8位）向/从数据输入/输出端子发送/接收数据。存储单元阵列中的每个存储单元可以对应于2n个阈值电平保存n位的数据。写入数据转换电路从以不同定时输入的多个j位数据的集合中的同一数据输入/输出端输入的位数据生成写入数据。

5. 发明申请

US20100044773A1 SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20100044773A1
公开(公告)日：2010-02-25
申请号：US12495093
申请日：2009-06-30
申请人： Yoshiyuki Ishigaki , Naoki Tsuji , Hisakazu Otoi , Hiroki Mukai , Yuichi Kunori
发明人： Yoshiyuki Ishigaki , Naoki Tsuji , Hisakazu Otoi , Hiroki Mukai , Yuichi Kunori
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/11546 , H01L29/42328 , H01L29/7881
摘要： To provide a semiconductor memory device having an improved write efficiency because deterioration of a gate insulating film is suppressed.An element formation region is formed in a region of a semiconductor substrate sandwiched between element isolation regions. In the element isolation regions, a silicon oxide film is filled in a trench having a predetermined depth. An erase gate electrode is formed in the element isolation region while being buried in the silicon oxide film. Over the element formation region, floating gate electrodes are formed via a gate oxide film and control gate electrodes are formed over the floating gate electrodes via an ONO film. Two adjacent floating gate electrodes have therebetween an insulating film formed to cover the erase gate electrode.
摘要翻译：提供一种由于栅极绝缘膜的劣化被抑制而具有提高的写入效率的半导体存储器件。元件形成区域形成在夹在元件隔离区域之间的半导体衬底的区域中。在元件隔离区域中，氧化硅膜填充在具有预定深度的沟槽中。在元件隔离区域中形成擦除栅电极，同时埋入氧化硅膜中。在元件形成区域上，通过栅极氧化膜形成浮栅，并且通过ONO膜在浮栅上形成控制栅电极。两个相邻的浮栅电极之间形成有覆盖擦除栅电极的绝缘膜。

6. 发明授权

US07433230B2 Nonvolatile semiconductor memory device having assist gate 失效
标题翻译：具有辅助门的非易失性半导体存储器件
公开(公告)号：US07433230B2
公开(公告)日：2008-10-07
申请号：US11411938
申请日：2006-04-27
申请人： Takashi Kono , Yuichi Kunori , Hironori Iga
发明人： Takashi Kono , Yuichi Kunori , Hironori Iga
IPC分类号： G11C11/34 , G11C5/06 , G11C7/00 , G11C8/99
CPC分类号： G11C16/0491 , G11C16/0433 , G11C16/24 , G11C16/26
摘要： In this AG-AND type flash memory, a layered bit line configuration where a memory array is divided into a plurality of sub blocks, new main bit lines are allocated so as to correspond to each sub block, and a main bit line is selectively connected to a global bit line in an upper layer via a switch is adopted, so that charge sharing write-in is carried out between two main bit lines. Accordingly, write-in of data into the flash memory can be carried out with low power consumption, and the threshold voltage can be controlled with precision.
摘要翻译：在该AG-AND型闪存中，分层位线配置将存储器阵列分成多个子块，分配新的主位线以便对应于每个子块，并且主位线被选择性地连接采用通过开关在上层的全局位线，从而在两个主位线之间执行电荷共享写入。因此，可以以低功耗进行数据写入闪速存储器，并且可以精确地控制阈值电压。

7. 发明授权

US07296111B2 Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing 有权
标题翻译：可实现高速数据读取和高速数据写入的多级存储非易失性半导体存储器件
公开(公告)号：US07296111B2
公开(公告)日：2007-11-13
申请号：US11414363
申请日：2006-05-01
申请人： Yuichi Kunori
发明人： Yuichi Kunori
IPC分类号： G06F12/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642
摘要： A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.
摘要翻译：非易失性半导体存储器件每j位（例如8位）向/从数据输入/输出端子发送/接收数据。存储单元阵列中的每个存储器单元可以保存与第二阈值电平对应的n位的数据。写入数据转换电路从以不同定时输入的多个j位数据的集合中的同一数据输入/输出端输入的位数据生成写入数据。

8. 发明申请

US20060158932A1 Nonvolatile semiconductor memory device having reduced dependency of a source resistance on a position in an array 有权
标题翻译：非易失性半导体存储器件具有降低源极电阻对阵列中位置的依赖性
公开(公告)号：US20060158932A1
公开(公告)日：2006-07-20
申请号：US11329036
申请日：2006-01-11
申请人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
发明人： Satoru Tamada , Yuichi Kunori , Fumihiko Nitta
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A dummy cell having a low threshold voltage is disposed in a memory cell array in alignment with a memory cell. A dummy cell with a low threshold voltage adjacent to a selected memory cell column is selected, and a source-side local bit line of the selected memory cell is coupled to a global bit line via such dummy cell. Since the source-side local bit line is coupled to a ground node at its both ends, source resistance of the memory cell can be reduced, and dependency of the source resistance of the memory cell on the position within the memory cell array can also be reduced. This allows for reducing dependency of source resistance of a memory cell on the position within the memory cell array and on the temperature in a nonvolatile semiconductor memory device.
摘要翻译：具有低阈值电压的虚拟单元被布置在与存储单元对准的存储单元阵列中。选择与所选存储单元列相邻的具有低阈值电压的虚拟单元，并且所选择的存储单元的源极局部位线通过这样的虚设单元耦合到全局位线。由于源极本地位线在其两端耦合到接地节点，所以可以减小存储器单元的源极电阻，并且存储单元的源极电阻对存储单元阵列内的位置的依赖性也可以是减少这允许减小存储器单元的源电阻对存储单元阵列内的位置和非易失性半导体存储器件中的温度的依赖性。

9. 发明授权

US08339850B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08339850B2
公开(公告)日：2012-12-25
申请号：US12766624
申请日：2010-04-23
申请人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
发明人： Hiroaki Tanizaki , Yuichi Kunori , Tomoshi Futatsuya , Kenji Koda
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06 , G11C5/14
CPC分类号： G11C16/3445 , G11C16/10 , G11C16/16 , G11C16/344 , G11C16/3454 , G11C16/3459 , G11C2216/22
摘要： The present invention provides a semiconductor device having a nonvolatile memory function capable of shortening an erase time and executing data access efficiently. When, under the control of a command register/control circuit, an erase voltage is applied to an embedded erase gate wiring disposed in a memory cell boundary region, and an electrical charge is transferred between a floating gate and an embedded erase gate to thereby perform an erase operation, a read selection voltage is applied to a memory gate line and an assist gate line during the application of the erase voltage to thereby carry out the reading of data.
摘要翻译：本发明提供一种具有能够缩短擦除时间并有效执行数据访问的非易失性存储功能的半导体器件。当在命令寄存器/控制电路的控制下，将擦除电压施加到布置在存储单元边界区域中的嵌入式擦除栅极布线，并且在浮动栅极和嵌入式擦除栅极之间传送电荷，从而执行擦除操作时，在施加擦除电压期间将读取选择电压施加到存储器栅极线和辅助栅极线，从而执行数据的读取。

10. 发明授权

US07949823B2 Multilevel storage nonvolatile semiconductor memory device enabling high-speed data reading and high-speed data writing 有权
标题翻译：可实现高速数据读取和高速数据写入的多级存储非易失性半导体存储器件
公开(公告)号：US07949823B2
公开(公告)日：2011-05-24
申请号：US12697852
申请日：2010-02-01
申请人： Yuichi Kunori
发明人： Yuichi Kunori
IPC分类号： G06F12/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5642
摘要： A nonvolatile semiconductor memory device transmits/receives data to/from a data input/output terminal every j bits (e.g., eight bits). Each of memory cells in a memory cell array can hold data of n bits in correspondence to 2n threshold levels. A write data conversion circuit generates write data from bit data input from the same data input/output terminal in a set of a plurality of data of j bits input at different timings.
摘要翻译：非易失性半导体存储器件每j位（例如8位）向/从数据输入/输出端子发送/接收数据。存储单元阵列中的每个存储单元可以对应于2n个阈值电平保存n位的数据。写入数据转换电路从以不同定时输入的多个j位数据的集合中的同一数据输入/输出端输入的位数据生成写入数据。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式