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1. 发明申请

US20050152204A1 Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays 有权
标题翻译：用于支持缓存和补充存储器阵列之间数据传输的FIFO应用程序中的多端口存储单元
公开(公告)号：US20050152204A1
公开(公告)日：2005-07-14
申请号：US10930966
申请日：2004-08-31
申请人： Shih-Ked Lee , Mario Au
发明人： Shih-Ked Lee , Mario Au
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines. A direct path data transfer circuit is provided. This transfer circuit is configured to support a unidirectional data transfer path that extends from first storage nodes within the first SRAM element to second storage nodes within the second dual-port SRAM element. This transfer circuit is also responsive to a direct path word line signal.
摘要翻译：多端口存储单元包括具有电耦合到一对FIFO写位线的第一对存取晶体管的第一SRAM元件。还提供了第二个双端口SRAM元件。该第二双端口SRAM元件具有电耦合到一对FIFO读位线的第二对存取晶体管和电耦合到一对存储器读位线的第三对存取晶体管。提供直接路径数据传输电路。该传送电路被配置为支持从第一SRAM元件内的第一存储节点延伸到第二双端口SRAM元件内的第二存储节点的单向数据传输路径。该传送电路也响应于直接路径字线信号。

2. 发明授权

US07042792B2 Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays 有权
标题翻译：用于支持缓存和补充存储器阵列之间数据传输的FIFO应用程序中的多端口存储单元
公开(公告)号：US07042792B2
公开(公告)日：2006-05-09
申请号：US10930966
申请日：2004-08-31
申请人： Shih-Ked Lee , Mario Au
发明人： Shih-Ked Lee , Mario Au
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines. A direct path data transfer circuit is provided. This transfer circuit is configured to support a unidirectional data transfer path that extends from first storage nodes within the first SRAM element to second storage nodes within the second dual-port SRAM element. This transfer circuit is also responsive to a direct path word line signal.
摘要翻译：多端口存储单元包括具有电耦合到一对FIFO写位线的第一对存取晶体管的第一SRAM元件。还提供了第二个双端口SRAM元件。该第二双端口SRAM元件具有电耦合到一对FIFO读位线的第二对存取晶体管和电耦合到一对存储器读位线的第三对存取晶体管。提供直接路径数据传输电路。该传送电路被配置为支持从第一SRAM元件内的第一存储节点延伸到第二双端口SRAM元件内的第二存储节点的单向数据传输路径。该传送电路也响应于直接路径字线信号。

3. 发明授权

US07870310B2 Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system 有权
标题翻译：多个计数器可以缓解多队列先进先出的内存系统中的标志限制
公开(公告)号：US07870310B2
公开(公告)日：2011-01-11
申请号：US11040892
申请日：2005-01-21
申请人： Mario Au , Jason Z. Mo
发明人： Mario Au , Jason Z. Mo
IPC分类号： G06F13/28 , G11C7/00 , G06F7/38
CPC分类号： G06F5/065 , G06F5/14 , G11C8/16
摘要： A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.
摘要翻译：一种操作多队列设备的方法，包括：（1）存储多个读取（写入）计数指针，其中读取（写入）计数指针中的每一个与多队列设备的相应队列相关联（ 2）提供与当前队列相关联的读取（写入）计数指针以读取（写入）标志逻辑，（3）响应于由每个读取（写入）操作执行的每个读取（写入）操作，调整与当前队列相关联的读取（写入）计数指针（4）指示从当前队列到下一队列的读（写）队列切换，（5）检索与下一队列相关联的读（写）计数指针; 然后（6）同时将与当前队列相关联的读（写）计数指针和与下一队列相关联的读（写）计数指针提供给读（写）标志逻辑。

4. 发明授权

US07269700B2 Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system 有权
标题翻译：在多队列先进先出存储器系统中，状态总线仅在循环模式操作期间仅访问可用象限
公开(公告)号：US07269700B2
公开(公告)日：2007-09-11
申请号：US11040893
申请日：2005-01-21
申请人： Mario Au , Jason Z. Mo , Cheng-Han Wu
发明人： Mario Au , Jason Z. Mo , Cheng-Han Wu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F3/00 , G11C7/10
CPC分类号： G06F5/065
摘要： A flag logic circuit is provided for use in a multi-queue memory device having a plurality of queues. A first stage memory stores a flag value for each of the queues in the multi-queue memory device. Flag values are routed from the first stage memory to a flag status bus having a width N in the manner described below. A status bus control circuit receives a signal that identifies the number of queues M actually used by the multi-queue memory device, and in response, generates a repeating pattern of X control values, wherein X is equal to (M−(M mod N))/N+1. A selector circuit sequentially routes X sets of N flag values from the first stage memory to the flag status bus in response to the repeating pattern of X control values. The X sets of N flag values include the flag values associated with the queues actually used.
摘要翻译：提供了一种用于具有多个队列的多队列存储装置中的标志逻辑电路。第一级存储器存储多队列存储器设备中的每个队列的标志值。标志值以下述方式从第一级存储器路由到具有宽度N的标志状态总线。状态总线控制电路接收识别由多队列存储装置实际使用的队列数M的信号，并且作为响应，生成X个控制值的重复模式，其中X等于（M-（M mod N ））/ N + 1。响应于X控制值的重复模式，选择器电路将X组N标志值从第一级存储器顺序地路由到标志状态总线。 X组N标志值包括与实际使用的队列相关联的标志值。

5. 发明授权

US07246300B1 Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation 有权
标题翻译：具有诊断位产生的具有错误检测和校正能力的顺序流量控制和FIFO存储器件
公开(公告)号：US07246300B1
公开(公告)日：2007-07-17
申请号：US10912938
申请日：2004-08-06
申请人： Mario Au , Jiann-Jeng Duh
发明人： Mario Au , Jiann-Jeng Duh
IPC分类号： H03M13/00
CPC分类号： G06F11/1064
摘要： FIFO memory devices include a multi-port cache memory device configured to generate a data word along with a plurality of diagnostic bits. These diagnostics bits encode an error correction status of the data word and a path traversal status of the data word through the FIFO memory device. In particular, the diagnostic bits identify all cases of whether the data word includes a corrected or uncorrected error, is without error or is unchecked for errors because the data word did not pass through error detection and correction circuitry within the FIFO memory device.
摘要翻译： FIFO存储器设备包括多端口高速缓存存储器设备，其配置成与多个诊断位一起生成数据字。这些诊断位通过FIFO存储器件对数据字的纠错状态和数据字的路径遍历状态进行编码。特别地，诊断位识别数据字是否包括校正或未校正的错误的所有情况，没有错误或由于数据字未通过FIFO存储器件内的错误检测和校正电路而导致错误。

6. 发明申请

US20060018177A1 Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system 有权
标题翻译：多个计数器可以缓解多队列先进先出的内存系统中的标志限制
公开(公告)号：US20060018177A1
公开(公告)日：2006-01-26
申请号：US11040892
申请日：2005-01-21
申请人： Mario Au , Jason Mo
发明人： Mario Au , Jason Mo
IPC分类号： G11C8/00
CPC分类号： G06F5/065 , G06F5/14 , G11C8/16
摘要： A method of operating a multi-queue device, including: (1) storing a plurality of read (write) count pointers, wherein each of the read (write) count pointers is associated with a corresponding queue of the multi-queue device, (2) providing a read (write) count pointer associated with a present queue to read (write) flag logic, (3) adjusting the read (write) count pointer associated with the present queue in response to each read (write) operation performed by the present queue, (4) indicating a read (write) queue switch from the present queue to a next queue, (5) retrieving a read (write) count pointer associated with the next queue; and then (6) simultaneously providing the read (write) count pointer associated with the present queue and the read (write) count pointer associated with the next queue to the read (write) flag logic.
摘要翻译：一种操作多队列设备的方法，包括：（1）存储多个读取（写入）计数指针，其中读取（写入）计数指针中的每一个与多队列设备的相应队列相关联（ 2）提供与当前队列相关联的读取（写入）计数指针以读取（写入）标志逻辑，（3）响应于由每个读取（写入）操作执行的每个读取（写入）操作，调整与当前队列相关联的读取（写入）计数指针（4）指示从当前队列到下一队列的读（写）队列切换，（5）检索与下一队列相关联的读（写）计数指针; 然后（6）同时将与当前队列相关联的读（写）计数指针和与下一队列相关联的读（写）计数指针提供给读（写）标志逻辑。

7. 发明授权

US06874064B2 FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability 有权
标题翻译：具有多端口缓存的FIFO存储器件和其中具有重传能力的扩展容量存储器件
公开(公告)号：US06874064B2
公开(公告)日：2005-03-29
申请号：US10818018
申请日：2004-04-05
申请人： Mario Au , Li-Yuan Chen
发明人： Mario Au , Li-Yuan Chen
IPC分类号： G06F5/10 , G11C7/10 , G06F12/08
CPC分类号： G11C7/1075 , G06F5/10 , G06F2205/062 , G06F2205/065
摘要： A FIFO memory device includes a multi-port cache memory and an extended capacity memory (e.g., SRAM). The multi-port cache memory includes a data input port, a data output port, a first memory port that is configured to pass write data to the extended capacity memory during memory write operations and a second memory port that is configured to receive read data from the extended capacity memory during memory read operations. The multi-port cache memory includes at least a data input register and a multiplexer that is responsive to at least one path signal. The multiplexer is configured to enable a first memory path that routes first data from the second memory port to the data output port during first FIFO read operations that occur when the FIFO memory device is filled beyond a threshold level. The multiplexer is also configured to block the first memory path and enable a direct path that routes second data from the data input register to the data output port during second FIFO read operations that occur when the FIFO memory device is almost empty.
摘要翻译： FIFO存储器件包括多端口高速缓冲存储器和扩展容量存储器（例如，SRAM）。多端口高速缓存存储器包括数据输入端口，数据输出端口，被配置为在存储器写入操作期间将写入数据传送到扩展容量存储器的第一存储器端口以及配置为从存储器写入操作中接收读取数据的第二存储器端口存储器读取操作期间的扩展容量存储器。多端口高速缓冲存储器至少包括数据输入寄存器和响应于至少一个路径信号的复用器。多路复用器被配置为使得当FIFO存储器设备被填充超过阈值水平时发生的第一FIFO读取操作期间，使第一存储器路径将第一数据从第二存储器端口路由到数据输出端口。多路复用器还被配置为阻止第一存储器路径，并且在FIFO存储器件几乎为空时发生的第二FIFO读操作期间启用从数据输入寄存器将数据路由到数据输出端口的直接路径。

8. 发明授权

US07805552B2 Partial packet write and write data filtering in a multi-queue first-in first-out memory system 有权
标题翻译：在多队列先进先出存储器系统中部分数据包写入和写入数据过滤
公开(公告)号：US07805552B2
公开(公告)日：2010-09-28
申请号：US11040896
申请日：2005-01-21
申请人： Mario Au , Jason Z. Mo , Hui Su
发明人： Mario Au , Jason Z. Mo , Hui Su
IPC分类号： G06F13/00 , G06F3/00 , G06F5/00
CPC分类号： G06F5/065 , G06F2205/108
摘要： A multi-queue memory system is configured to operate in a packet mode. Each packet includes a SOP (start of packet) marker and an EOP (end of packet) marker. A packet status bit (PSB), is used to implement the packet mode. The packet status bit enables partial packet write and partial packet read operations, such that a queue switch can be performed in the middle of packet write or packet read operations. The packet status bit also enables data filtering to be performed between an activated EOP marker and a subsequently received SOP marker (i.e., between the end of one packet and the start of the next packet). Packet mark and re-write and packet mark and re-read operations are also enabled.
摘要翻译：多队列存储器系统被配置为以分组模式操作。每个分组包括SOP（分组开始）标记和EOP（分组结束）标记。分组状态位（PSB）用于实现分组模式。分组状态位使得能够进行部分分组写入和部分分组读取操作，使得可以在分组写入或分组读取操作的中间执行队列切换。分组状态位还使得能够在激活的EOP标记和随后接收的SOP标记（即，在一个分组的结束和下一个分组的开始之间）之间执行数据过滤。数据包标记和重写以及数据包标记和重新读取操作也被启用。

9. 发明申请

US20060017497A1 Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system 有权
公开(公告)号：US20060017497A1
公开(公告)日：2006-01-26
申请号：US11040927
申请日：2005-01-21
申请人： Jason Mo , Mario Au
发明人： Jason Mo , Mario Au
IPC分类号： H03B1/00
CPC分类号： G11C19/287
摘要： A write counter provides a write count value synchronized with a write clock signal. A read counter provides a read count value synchronized with a read clock signal. The read and write count values are routed through logic, which introduces noise to these values. A first delay circuit generates a first blanking signal, which has a duration corresponding with the duration of the noise introduced to the write count value, in response to the write clock signal. A second delay circuit generates a second blanking signal, which has a duration corresponding with the duration of the noise introduced to the read count value, in response to the second clock signal. The read and write count values are latched into read and write blanking registers, respectively, in response to the first and second blanking signals, respectively, effectively filtering the introduced noise prior to a subsequently performed comparison operation.

10. 发明申请

US20050184768A1 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US20050184768A1
公开(公告)日：2005-08-25
申请号：US11009434
申请日：2004-12-09
申请人： David Pilling , Kar-chung Lee , Mario Au
发明人： David Pilling , Kar-chung Lee , Mario Au
IPC分类号： H03B1/00 , H03K19/003 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

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