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1. 发明授权

US07400026B2 Thin film resistor structure 有权
标题翻译：薄膜电阻器结构
公开(公告)号：US07400026B2
公开(公告)日：2008-07-15
申请号：US11342134
申请日：2006-01-26
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的导电层。沉积一层氮化钛，并在氧气氛中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。

2. 发明授权

US07078306B1 Method for forming a thin film resistor structure 失效
标题翻译：用于形成薄膜电阻器结构的方法
公开(公告)号：US07078306B1
公开(公告)日：2006-07-18
申请号：US10805718
申请日：2004-03-22
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L21/20
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a method for forming a thin film resistor and a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a portion of the gate structure. A layer of titanium nitride is deposited using a chemical vapor deposition process. A rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure. A metal layer is deposited and patterned to form an interconnect structure that electrically couples the titanium oxynitride structure to other circuitry.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器和薄膜电阻器的形成方法。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的一部分。使用化学气相沉积工艺沉积一层氮化钛。在氧环境中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。金属层被沉积并图案化以形成将氮氧化钛结构电耦合到其它电路的互连结构。

3. 发明申请

US20060118910A1 Thin film resistor structure 有权
标题翻译：薄膜电阻器结构
公开(公告)号：US20060118910A1
公开(公告)日：2006-06-08
申请号：US11342134
申请日：2006-01-26
申请人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
发明人： Gaolong Jin , Wanqing Cao , Guo-Qiang Lo , Shih-Ked Lee
IPC分类号： H01L29/00
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention relates to a thin film resistor formed over a semiconductor substrate. A gate structure is formed and a dielectric layer is formed over the gate structure. A via is then etched that extends through the dielectric layer so as to expose a conductive layer of the gate structure. A layer of titanium nitride is deposited A and a rapid thermal anneal is performed in an oxygen ambient. The rapid thermal anneal incorporates oxygen into the titanium nitride, forming titanium oxynitride film. A layer of dielectric material is then deposited and etched-back to form a dielectric plug that fills the remaining portion of the via. The titanium oxynitride film is patterned to form a titanium oxynitride structure that is electrically coupled to the gate structure.
摘要翻译：本发明涉及形成在半导体衬底上的薄膜电阻器。形成栅极结构，并且在栅极结构上形成介电层。然后蚀刻通孔，其延伸穿过电介质层，以暴露栅极结构的导电层。淀积一层氮化钛，并在氧气氛中进行快速热退火。快速热退火将氧气纳入氮化钛中，形成氮氧化钛膜。然后沉积介电材料层并将其蚀刻回来形成填充通孔的剩余部分的电介质塞子。将氮氧化钛膜图案化以形成电耦合到栅极结构的氮氧化钛结构。

4. 发明授权

US06627543B1 Low-temperature sputtering system and method for salicide process 失效
标题翻译：低温溅射系统和自杀剂方法
公开(公告)号：US06627543B1
公开(公告)日：2003-09-30
申请号：US09564304
申请日：2000-05-03
申请人： Wanqing Cao , Guo-Qiang Patrick Lo , Shih-Ked Lee , Robert B. Hixson , Eric S. Lee
发明人： Wanqing Cao , Guo-Qiang Patrick Lo , Shih-Ked Lee , Robert B. Hixson , Eric S. Lee
IPC分类号： H01L2144
CPC分类号： H01L21/28518 , H01L21/2855
摘要： Disclosed are methods and systems for forming salicide, in which a semiconductor substrate is provided with at least one exposed silicon surface. The semiconductor substrate is placed into a sputtering chamber. A silicide-forming metal layer, formed of a metal such as Co, Ni, is sputter-deposited over the exposed silicon surface. A process temperature is controlled below room temperature during the sputter deposition and preferably between approximately 0° C. to 10° C. The silicide-forming metal layer formed on the exposed silicon surface is first annealed to convert the silicide-forming metal layer into a salicide layer. Also, the system of the present invention is comprised of a sputter chamber including a mount for mounting a semiconductor substrate and a cooling mechanism coupled with the mount for cooling the semiconductor substrate. The cooling mechanism includes a controller to maintain a process temperature below room temperature. Improved device characteristics such as increased charge-to-breakdown can be achieved in the devices according to the present invention compared to the devices with high-temperature sputtered salicide.
摘要翻译：公开了用于形成硅化物的方法和系统，其中半导体衬底设置有至少一个暴露的硅表面。将半导体衬底放置在溅射室中。由诸如Co，Ni的金属形成的硅化物形成金属层溅射沉积在暴露的硅表面上。在溅射沉积期间将工艺温度控制在室温以下，优选在约0℃至10℃之间。形成在暴露的硅表面上的硅化物形成金属层首先退火，以将硅化物形成金属层转变为自杀层而且，本发明的系统包括一个包括一个用于安装一个半导体衬底的安装座和一个冷却机构的溅射室，该冷却机构与用于冷却半导体衬底的安装座相连。冷却机构包括将工艺温度保持在室温以下的控制器。与具有高温溅射的自对准硅化物的装置相比，在根据本发明的装置中可以实现改进的装置特性，例如增加的电荷到击穿电压。

5. 发明授权

US5990009A Maximization of low dielectric constant material between interconnect traces of a semiconductor circuit 失效
标题翻译：半导体电路的互连迹线之间的低介电常数材料的最大化
公开(公告)号：US5990009A
公开(公告)日：1999-11-23
申请号：US805607
申请日：1997-02-25
申请人： Cheng-Chen Hsueh , Shih-Ked Lee , Chuen-Der Lien
发明人： Cheng-Chen Hsueh , Shih-Ked Lee , Chuen-Der Lien
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/302
CPC分类号： H01L23/5329 , H01L21/76834 , H01L23/5222 , H01L2924/0002 , Y10S257/908
摘要： A structure and method of maximizing the volume of low dielectric constant material between adjacent traces of a conductive interconnect structure. A semiconductor structure includes a semiconductor substrate, a first insulating layer located over the semiconductor substrate, a conductive interconnect layer having a plurality of conductive traces located over the first insulating layer, and a patterned insulating layer located over the patterned interconnect layer. One or more trenches are formed in the upper surface of the first insulating layer. These trenches, which do not extend completely through the first insulating layer, are located between adjacent traces of the interconnect layer. A dielectric material having a low dielectric constant is located in these trenches, and between adjacent traces of the patterned interconnect layer. The trenches advantageously maximize the volume of low dielectric constant material which is located between the traces.
摘要翻译：一种使导电互连结构的相邻迹线之间的低介电常数材料的体积最大化的结构和方法。半导体结构包括半导体衬底，位于半导体衬底上的第一绝缘层，具有位于第一绝缘层上方的多个导电迹线的导电互连层以及位于图案化互连层上方的图案化绝缘层。一个或多个沟槽形成在第一绝缘层的上表面中。这些不完全延伸穿过第一绝缘层的沟槽位于互连层的相邻迹线之间。具有低介电常数的介电材料位于这些沟槽中，并位于图案化互连层的相邻迹线之间。沟槽有利地使位于迹线之间的低介电常数材料的体积最大化。

6. 发明授权

US07499303B2 Binary and ternary non-volatile CAM 有权
标题翻译：二进制和三元非易失性CAM
公开(公告)号：US07499303B2
公开(公告)日：2009-03-03
申请号：US10950186
申请日：2004-09-24
申请人： Chuen-Der Lien , Shih-Ked Lee
发明人： Chuen-Der Lien , Shih-Ked Lee
IPC分类号： G11C15/00
CPC分类号： G11C15/046 , G11C11/22 , G11C13/0004 , G11C15/02
摘要： A CAM cell array according to embodiments of the present invention include an array of CAM cells, each of the CAM cells comprising a first cell, the first cell including a non-volatile storage element coupled to at least one first data line and a match line; a match line controller coupled to the match line; and a data line controller coupled to the data lines, wherein a write operation is performed by changing a state of the non-volatile storage element by providing data to the at least one data line, wherein a read operation is performed by determining the state of the non-volatile storage element through the at least one data line, and wherein a comparison operation is performed by applying data to the at least one data line and determining a match condition on the match line.
摘要翻译：根据本发明的实施例的CAM单元阵列包括CAM单元的阵列，每个CAM单元包括第一单元，第一单元包括耦合到至少一个第一数据线和匹配线的非易失性存储元件 ; 耦合到匹配线的匹配线控制器; 以及耦合到数据线的数据线控制器，其中通过向所述至少一个数据线提供数据来改变所述非易失性存储元件的状态来执行写入操作，其中通过确定所述非易失性存储元件的状态来执行读取操作所述非易失性存储元件通过所述至少一个数据线，并且其中通过将数据应用于所述至少一条数据线并确定所述匹配线上的匹配条件来执行比较操作。

7. 发明授权

US07214990B1 Memory cell with reduced soft error rate 有权
标题翻译：具有降低的软错误率的存储单元
公开(公告)号：US07214990B1
公开(公告)日：2007-05-08
申请号：US11063704
申请日：2005-02-22
申请人： Shih-Ked Lee , Chuen-Der Lien , Louis Huang , Gaolong Jin , Wanqing Cao , Guo-Qiang Lo
发明人： Shih-Ked Lee , Chuen-Der Lien , Louis Huang , Gaolong Jin , Wanqing Cao , Guo-Qiang Lo
IPC分类号： H01L27/11
CPC分类号： H01L28/24 , H01L27/016 , H01L27/0802 , H01L29/78
摘要： The present invention includes SRAM memory cells and methods for forming SRAM cells having reduced soft error rate. The SRAM cell includes a first NMOS transistor and a first PMOS transistor having a common gate, and a second NMOS transistor and a second PMOS transistor having a common gate. A first resistor is electrically coupled on one end to the drains of the first PMOS transistor and the first NMOS transistor; and is electrically coupled on the other end to the common gate of the second NMOS and second PMOS transistors. A second resistor is electrically coupled on one end to the drains of the second PMOS transistor and the second NMOS transistor; and is electrically coupled on the other end to the common gate of the first NMOS transistor and the first PMOS transistor. The added resistor can be embedded in a contact opening such that it does not take up valuable surface area on the semiconductor substrate. Thereby, data loss from soft errors can be avoided while preserving small memory cell size.
摘要翻译：本发明包括SRAM存储单元和用于形成具有降低的软错误率的SRAM单元的方法。 SRAM单元包括第一NMOS晶体管和具有公共栅极的第一PMOS晶体管，以及具有公共栅极的第二NMOS晶体管和第二PMOS晶体管。第一电阻器的一端电耦合到第一PMOS晶体管和第一NMOS晶体管的漏极; 并且在另一端电耦合到第二NMOS和第二PMOS晶体管的公共栅极。第二电阻器的一端电耦合到第二PMOS晶体管和第二NMOS晶体管的漏极; 并且在另一端电耦合到第一NMOS晶体管和第一PMOS晶体管的公共栅极。添加的电阻器可以嵌入在接触开口中，使得其不占据半导体衬底上的有价值的表面积。因此，可以避免从软错误的数据丢失，同时保持小的存储单元尺寸。

8. 发明申请

US20050152204A1 Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays 有权
标题翻译：用于支持缓存和补充存储器阵列之间数据传输的FIFO应用程序中的多端口存储单元
公开(公告)号：US20050152204A1
公开(公告)日：2005-07-14
申请号：US10930966
申请日：2004-08-31
申请人： Shih-Ked Lee , Mario Au
发明人： Shih-Ked Lee , Mario Au
IPC分类号： G11C8/00
CPC分类号： G11C8/16
摘要： A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access transistors electrically coupled to a pair of FIFO read bit lines and a third pair of access transistors electrically coupled to a pair of memory read bit lines. A direct path data transfer circuit is provided. This transfer circuit is configured to support a unidirectional data transfer path that extends from first storage nodes within the first SRAM element to second storage nodes within the second dual-port SRAM element. This transfer circuit is also responsive to a direct path word line signal.
摘要翻译：多端口存储单元包括具有电耦合到一对FIFO写位线的第一对存取晶体管的第一SRAM元件。还提供了第二个双端口SRAM元件。该第二双端口SRAM元件具有电耦合到一对FIFO读位线的第二对存取晶体管和电耦合到一对存储器读位线的第三对存取晶体管。提供直接路径数据传输电路。该传送电路被配置为支持从第一SRAM元件内的第一存储节点延伸到第二双端口SRAM元件内的第二存储节点的单向数据传输路径。该传送电路也响应于直接路径字线信号。

9. 发明授权

US06791155B1 Stress-relieved shallow trench isolation (STI) structure and method for forming the same 有权
标题翻译：应力消除浅沟槽隔离（STI）结构及其形成方法
公开(公告)号：US06791155B1
公开(公告)日：2004-09-14
申请号：US10251550
申请日：2002-09-20
申请人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
发明人： Guo-Qiang (Patrick) Lo , Brian Schorr , Gary Foley , Shih-Ked Lee
IPC分类号： H01L2176
CPC分类号： H01L21/764 , H01L21/76224
摘要： A shallow trench isolation (STI) structure in a semiconductor substrate and a method for forming the same are provided. A trench is formed in a semiconductor substrate. A first dielectric layer is formed on sidewalls of the trench. The first dielectric layer is formed thicker at a top portion of the sidewalls than a bottom portion of the sidewalls and leaving an entrance of the trench open to expose the trench. A second dielectric layer is conformally formed on the first dielectric layer to close the entrance, thus forming a void buried within the trench. Thus, the stress between the trench dielectric layer and the surrounding silicon substrate during thermal cycling can be substantially reduced.
摘要翻译：提供半导体衬底中的浅沟槽隔离（STI）结构及其形成方法。在半导体衬底中形成沟槽。第一电介质层形成在沟槽的侧壁上。第一电介质层在侧壁的顶部处形成得比侧壁的底部更厚，并且使沟槽的入口敞开以暴露沟槽。在第一电介质层上共形形成第二电介质层以封闭入口，从而形成埋在沟槽内的空隙。因此，可以显着地减少在热循环期间沟槽电介质层和周围硅衬底之间的应力。

10. 发明授权

US06306771B1 Process for preventing the formation of ring defects 有权
标题翻译：防止环形缺陷形成的方法
公开(公告)号：US06306771B1
公开(公告)日：2001-10-23
申请号：US09384752
申请日：1999-08-27
申请人： Tsengyou Syau , James R. Shih , Shih-Ked Lee , Timothy P. Kay
发明人： Tsengyou Syau , James R. Shih , Shih-Ked Lee , Timothy P. Kay
IPC分类号： H01L21302
CPC分类号： H01L21/32139 , H01L21/32136
摘要： The prevention of the formation of undesired defects formed during the etching of etched metal interconnect lines on an integrated circuit during an integrated circuit manufacturing process that involves laying down on a semiconductor wafer a thin film such as an anti-reflective coating (ARC) on a layer of metal to be patterned into the metal interconnects of the individual integrated circuits. To do this the anti-reflective coating layer is covered with an oxide layer prior to applying and patterning subsequent photoresist. The specific metalization layer disclosed can be of aluminum, copper or copper-aluminum alloy. The ARC as disclosed is a nitride layer, such as titanium nitride. The oxide may be formed on the ARC in a number of known ways and may be etched subsequently alone or in combination with the underlying ARC and metal after subsequent photoresist deposit upon the oxide layer.
摘要翻译：在集成电路制造过程中防止在集成电路制造过程中在蚀刻金属互连线上的蚀刻金属互连线时形成的不希望的缺陷的形成，其包括在半导体晶片上放置诸如抗反射涂层（ARC）的薄膜金属层将被图案化成各个集成电路的金属互连。为了做到这一点，在施加和图形化随后的光致抗蚀剂之前，抗氧化层被氧化物层覆盖。所公开的具体金属化层可以是铝，铜或铜 - 铝合金。所公开的ARC是氮化物层，例如氮化钛。氧化物可以以多种已知方式形成在ARC上，并且随后光致抗蚀剂沉积在氧化物层上之后可以单独蚀刻或与下面的ARC和金属组合进行蚀刻。

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