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1. 发明申请

US20070285135A1 Output drive circuit that accommodates variable supply voltages 有权
公开(公告)号：US20070285135A1
公开(公告)日：2007-12-13
申请号：US11800438
申请日：2007-05-04
申请人： David Pilling , Kar-chung Lee , Mario Au
发明人： David Pilling , Kar-chung Lee , Mario Au
IPC分类号： H03B1/00
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.

2. 发明申请

US20050184768A1 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US20050184768A1
公开(公告)日：2005-08-25
申请号：US11009434
申请日：2004-12-09
申请人： David Pilling , Kar-chung Lee , Mario Au
发明人： David Pilling , Kar-chung Lee , Mario Au
IPC分类号： H03B1/00 , H03K19/003 , H03K19/017 , H03K19/0185
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

3. 发明申请

US20050206426A1 Integrated circuit systems and devices having high precision digital delay lines therein 失效
标题翻译：其中具有高精度数字延迟线的集成电路系统和装置
公开(公告)号：US20050206426A1
公开(公告)日：2005-09-22
申请号：US11134899
申请日：2005-05-23
申请人： Robert Proebsting , Cesar Talledo , David Pilling
发明人： Robert Proebsting , Cesar Talledo , David Pilling
IPC分类号： G11C7/00 , H03H11/26 , H03K3/03 , H03K5/00 , H03K5/13 , H03K5/135 , H03L7/081
CPC分类号： H03H11/265 , H03K3/0322 , H03K5/133 , H03K5/135 , H03K2005/00032 , H03K2005/00104 , H03K2005/00208 , H03K2005/00247 , H03K2005/00286 , H03L7/0812
摘要： An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the delay. A delay line control circuit is also provided. The delay line control circuit is configured to generate the control signal by counting multiple cycles of a high frequency oscillator signal (e.g., ring oscillator signal) having a period less than the clock period, over a time interval having a duration greater than the clock period.
摘要翻译：集成电路延迟装置包括数字延迟线，其被配置为响应于控制信号向在其输入处接收的定时信号提供百分比时钟周期延迟。该控制信号具有指定延迟长度的值。还提供延迟线控制电路。延迟线控制电路被配置为通过在具有大于时钟周期的持续时间的时间间隔内对具有小于时钟周期的周期的高频振荡器信号（例如，环形振荡器信号）的多个周期进行计数来生成控制信号。

4. 发明授权

US07586343B2 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US07586343B2
公开(公告)日：2009-09-08
申请号：US11800438
申请日：2007-05-04
申请人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
发明人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

5. 发明申请

US20050128664A1 Circuits and methods that attenuate coupled noise 有权
标题翻译：衰减耦合噪声的电路和方法
公开(公告)号：US20050128664A1
公开(公告)日：2005-06-16
申请号：US10982128
申请日：2004-11-05
申请人： David Pilling , James Fox , Ken Chan
发明人： David Pilling , James Fox , Ken Chan
IPC分类号： H01L23/50 , H01L23/60 , H01L27/02 , H02H9/00
CPC分类号： H01L27/0251 , H01L23/50 , H01L23/60 , H01L2224/48091 , H01L2224/49113 , H01L2924/10253 , H01L2924/19041 , H01L2924/30107 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： Systems and methods of chip design and package implementation for attenuating noise in timing circuits, including phase-locked-loops (PLL) and delay-locked-loops (DLL), are disclosed. Embodiments of the present invention attenuate coupled noise, such as the effects of ground current surges, or power supply noise coupling through electro-static discharge (ESD) structures. In known systems, the ground supplies for the timing circuits are designed with power and ground supplies, separate from the core power and ground; although the ground supplies are connected via common VSSsubstrate, they are separated from pad ring output driver power and ground supplies. In embodiments of the present invention, the PLL or DLL and core supplies are kept separate from the output driver power and ground supplies, providing for improved systems and methods that attenuate the effects of ground current surges from chip output drivers as they switch from logic highs to logic lows.
摘要翻译：公开了用于衰减定时电路中的噪声的芯片设计和封装实现的系统和方法，包括锁相环（PLL）和延迟锁定环（DLL）。本发明的实施例通过静电放电（ESD）结构来衰减耦合噪声，例如接地电流浪涌的影响或电源噪声耦合。在已知系统中，定时电路的接地电源设计有电源和地电源，与核心电源和地线分开; 虽然接地电源通过公共的SS SS衬底连接，但是它们与焊盘环输出驱动器电源和接地电源分离。在本发明的实施例中，PLL或DLL和核心电源与输出驱动器电源和接地电源保持分开，从而提供改进的系统和方法，其从芯片输出驱动器切换到逻辑高电平时削弱地电流浪涌的影响到逻辑低点。

6. 发明授权

US07224195B2 Output drive circuit that accommodates variable supply voltages 有权
标题翻译：输出驱动电路，适应可变电源电压
公开(公告)号：US07224195B2
公开(公告)日：2007-05-29
申请号：US11009434
申请日：2004-12-09
申请人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
发明人： David Pilling , Kar-chung Leo Lee , Mario Fulam Au
IPC分类号： H03B1/10 , H03K3/00
CPC分类号： H03K19/01707 , H03K19/00315 , H03K19/018585
摘要： In accordance with the invention, a driver circuit is described that permits a single thin gate oxide process to be utilized where a dual oxide process may normally be necessary. Circuits employing only thin gate oxide devices are used as the design basis for a single product with a single set of tooling and manufacturing process to operate within the same timing specifications for a core voltage output drive as well as for a higher system drive.
摘要翻译：根据本发明，描述了驱动器电路，其允许在通常需要双重氧化工艺的情况下利用单个薄栅氧化层工艺。仅使用薄栅极氧化器件的电路被用作单个产品的设计基础，具有单组工具和制造工艺，以在核心电压输出驱动器以及较高系统驱动器的相同时序规范内运行。

7. 发明申请

US20060190790A1 In-situ monitor of process and device parameters in integrated circuits 有权
公开(公告)号：US20060190790A1
公开(公告)日：2006-08-24
申请号：US11064038
申请日：2005-02-22
申请人： David Pilling , Cesar Talledo
发明人： David Pilling , Cesar Talledo
IPC分类号： G01R31/28
CPC分类号： G01R31/2882 , G01R31/2853 , G01R31/318541 , G01R31/318555 , G11C29/1201 , G11C29/48
摘要： In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

8. 发明申请

US20060190785A1 In-situ monitor of process and device parameters in integrated circuits 有权
公开(公告)号：US20060190785A1
公开(公告)日：2006-08-24
申请号：US11142758
申请日：2005-05-31
申请人： David Pilling
发明人： David Pilling
IPC分类号： G01R31/28
CPC分类号： G01R31/2853 , G01R31/2882 , G01R31/318541 , G01R31/318555 , G11C29/1201 , G11C29/48
摘要： In accordance with the invention, a testing circuit formed on the integrated circuit is presented. A testing circuit according to the present invention is coupled to a scan path circuit and includes an input circuit coupled to a parameter testing circuit and an output driver coupled to the parameter testing circuit. Embodiments of the parameter testing circuit can include circuits for testing process, device, and circuit characteristics of the integrated circuit. Further, some embodiments of the testing circuit can be included in a scan path system where sequences of various testing circuits are included. Further, test parameters obtained from the parameter testing circuits can be utilized to adjust operating parameters of the integrated circuit.

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