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1. 发明授权

US07226504B2 Method to form thick relaxed SiGe layer with trench structure 失效
标题翻译：形成具有沟槽结构的厚松弛SiGe层的方法
公开(公告)号：US07226504B2
公开(公告)日：2007-06-05
申请号：US10062336
申请日：2002-01-31
申请人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
发明人： Jer-Shen Maa , Douglas James Tweet , Tingkai Li , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B33/02
CPC分类号： H01L21/3247 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02694 , H01L21/324
摘要： A method of forming a SiGe layer having a relatively high germanium content and a relatively low threading dislocation density includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the germanium content of the SiGe layer is greater than 20%, by atomic ratio; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; patterning the SiGe layer with photoresist; plasma etching the structure to form trenches about regions; removing the photoresist; and thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes.
摘要翻译：形成具有较高锗含量和较低穿透位错密度的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的锗含量按原子比大于20％; 将H +离子以约1.10×16cm -2至0.0010±0.2cm的剂量注入SiGe层中， SUP>，在约20keV至45keV之间的能量; 用光致抗蚀剂图案化SiGe层; 等离子体蚀刻结构以形成关于区域的沟槽; 去除光致抗蚀剂; 以及对基板和SiGe层进行热退火，以在惰性气氛中在约650℃至950℃的温度下放置SiGe层约30秒至30分钟。

2. 发明申请

US20080164577A1 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US20080164577A1
公开(公告)日：2008-07-10
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L29/06
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒的阵列，并且在二氧化硅棒周围形成Si 3 N 4 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4 N 4管子下面的Si管。最后，去除Si 3 N 4 N 4管。

3. 发明授权

US07378286B2 Semiconductive metal oxide thin film ferroelectric memory transistor 有权
标题翻译：半导体金属氧化物薄膜铁电存储晶体管
公开(公告)号：US07378286B2
公开(公告)日：2008-05-27
申请号：US10922712
申请日：2004-08-20
申请人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
发明人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
IPC分类号： H01L29/72
CPC分类号： H01L29/7869 , H01L29/516 , H01L29/66545 , H01L29/66553 , H01L29/78621
摘要： The present invention discloses a novel transistor structure employing semiconductive metal oxide as the transistor conductive channel. By replacing the silicon conductive channel with a semiconductive metal oxide channel, the transistors can achieve simpler fabrication process and could realize 3D structure to increase circuit density. The disclosed semiconductive metal oxide transistor can have great potential in ferroelectric non volatile memory device with the further advantages of good interfacial properties with the ferroelectric materials, possible lattice matching with the ferroelectric layer, reducing or eliminating the oxygen diffusion problem to improve the reliability of the ferroelectric memory transistor. The semiconductive metal oxide film is preferably a metal oxide exhibiting semiconducting properties at the transistor operating conditions, for example, In2O3 or RuO2. The present invention ferroelectric transistor can be a metal-ferroelectric-semiconductive metal oxide FET having a gate stack of a top metal electrode disposed on a ferroelectric layer disposed on a semiconductive metal oxide channel on a substrate. Using additional layer of bottom electrode and gate dielectric, the present invention ferroelectric transistor can also be a metal-ferroelectric-metal (optional)-gate dielectric (optional)-semiconductive metal oxide FET.
摘要翻译：本发明公开了一种采用半导体金属氧化物作为晶体管导电通道的新型晶体管结构。通过用半导体金属氧化物沟道代替硅导电通道，晶体管可以实现更简单的制造工艺，并且可以实现3D结构以增加电路密度。所公开的半导体金属氧化物晶体管可以在铁电非易失性存储器件中具有很大的潜力，具有与铁电材料良好的界面性质，与铁电层的可能的晶格匹配，减少或消除氧扩散问题以提高可靠性的另外的优点铁电存储晶体管。半导体金属氧化物膜优选是在晶体管工作条件下表现出半导体性质的金属氧化物，例如在二氧化铈或RuO 2 。本发明的铁电晶体管可以是金属铁电半导体金属氧化物FET，其具有设置在设置在基板上的半导体金属氧化物沟道上的铁电层上的顶部金属电极的栅极堆叠。使用附加的底部电极和栅极电介质层，本发明的铁电晶体管也可以是金属 - 铁电 - 金属（可选） - 门电介质（可选） - 导电金属氧化物FET。

4. 发明授权

US07514282B2 Patterned silicon submicron tubes 失效
标题翻译：图案硅亚微米管
公开(公告)号：US07514282B2
公开(公告)日：2009-04-07
申请号：US11649634
申请日：2007-01-04
申请人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
发明人： Tingkai Li , Jong-Jan Lee , Jer-Shen Maa , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L21/306 , H01L29/0669 , H01L29/0673 , Y10S977/743
摘要： An array of submicron silicon (Si) tubes is provided with a method for patterning submicron Si tubes. The method provides a Si substrate, and forms a silicon dioxide film overlying the Si substrate. An array of silicon dioxide rods is formed from the silicon dioxide film, and Si3N4 tubes are formed surrounding the silicon dioxide rods. The silicon dioxide rods are etched away. Then, exposed regions of the Si substrate are etched, forming Si tubes underlying the Si3N4 tubes. Finally, the Si3N4 tubes are removed.
摘要翻译：亚微米硅（Si）管的阵列具有用于构图亚微米Si管的方法。该方法提供Si衬底，并形成覆盖Si衬底的二氧化硅膜。由二氧化硅膜形成二氧化硅棒阵列，在二氧化硅棒周围形成Si 3 N 4管。二氧化硅棒被蚀刻掉。然后，蚀刻Si衬底的暴露区域，形成Si 3 N 4管下面的Si管。最后，去除Si3N4管。

5. 发明申请

US20070278574A1 Compound semiconductor-on-silicon wafer with a thermally soft insulator 审中-公开
标题翻译：具有热软绝缘体的复合半导体硅片
公开(公告)号：US20070278574A1
公开(公告)日：2007-12-06
申请号：US11443144
申请日：2006-05-30
申请人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
发明人： Sheng Teng Hsu , Tingkai Li , Jong-Jan Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02488 , H01L21/02505 , H01L21/02529 , H01L21/02538 , H01L21/7624
摘要： A method is provided for forming a compound semiconductor-on-silicon (Si) wafer with a thermally soft insulator. The method forms a Si substrate, with a thermally soft insulator layer overlying the Si substrate. A silicon oxide layer is formed immediately overlying the thermally soft insulator layer, a top Si layer overlies the silicon oxide, and a lattice mismatch buffer layer overlies the top Si layer. A compound semiconductor layer is formed overlying the lattice mismatch buffer layer. The thermally soft insulator has a liquid phase temperature lower than the liquid phase temperatures of Si and the compound semiconductor. For example, the thermally soft insulator may have a flow temperature in the range of about 500° C. to 900° C., where the flow temperature is greater than the solid phase temperature and less than the liquid phase temperature.
摘要翻译：提供了一种用热软性绝缘体形成硅化合物半导体（Si）晶片的方法。该方法形成Si衬底，具有覆盖Si衬底的热软绝缘层。形成刚好覆盖在热软绝缘体层上的氧化硅层，顶部Si层覆盖在氧化硅上，并且晶格失配缓冲层覆盖在顶部Si层上。形成覆盖晶格失配缓冲层的化合物半导体层。该热软绝缘体的液相温度低于Si和化合物半导体的液相温度。例如，热软绝缘体可以具有在约500℃至900℃的范围内的流动温度，其中流动温度大于固相温度并且小于液相温度。

6. 发明授权

US07675056B2 Germanium phototransistor with floating body 有权
标题翻译：具有浮体的锗光电晶体管
公开(公告)号：US07675056B2
公开(公告)日：2010-03-09
申请号：US11891574
申请日：2007-08-10
申请人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
发明人： Jong-Jan Lee , Sheng Teng Hsu , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136 , H01L31/028 , H01L31/1808 , Y02E10/547
摘要： A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.
摘要翻译：提出了一种浮体锗（Ge）光电晶体管及其制造工艺。该方法包括：提供硅（Si）衬底; 选择性地形成覆盖Si衬底的绝缘体层; 使用液相外延（LPE）工艺形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成覆盖所述沟道区的栅极电介质，栅电极和栅极间隔; 并且在Ge层中形成源/漏区。 LPE工艺包括用具有大于第一温度的熔化温度的材料包封Ge，并且使用低于第一温度的温度来熔化Ge。 LPE工艺包括：形成覆盖沉积Ge的介电层; 融化Ge; 并且响应于冷却Ge，将外延生长前沿从下面的Si衬底表面横向传播到Ge中。

7. 发明授权

US07608874B2 Fully isolated photodiode stack 失效
标题翻译：全隔离光电二极管堆叠
公开(公告)号：US07608874B2
公开(公告)日：2009-10-27
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

8. 发明授权

US07438759B2 Ambient environment nanowire sensor 失效
公开(公告)号：US07438759B2
公开(公告)日：2008-10-21
申请号：US11264113
申请日：2005-11-01
申请人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
发明人： Fengyan Zhang , Robert A. Barrowcliff , Jong-Jan Lee , Sheng Teng Hsu
IPC分类号： C30B1/02
CPC分类号： B81C1/00182 , B81B2201/0214 , Y10S977/712 , Y10S977/762
摘要： An ambient environment nanowire sensor and corresponding fabrication method have been provided. The method includes: forming a substrate such as Silicon (Si) or glass; growing nanowires; depositing an insulator layer overlying the nanowires; etching to expose tips of the nanowires; forming a patterned metal electrode, with edges, overlying the tips of the nanowires; and, etching to expose the nanowires underlying the electrode edges. The nanowires can be a material such as IrO2, TiO2, InO, ZnO, SnO2, Sb2O3, or In2O3, to mane just a few examples. The insulator layer can be a spin-on glass (SOG) or low-k dielectric. In one aspect, the resultant structure includes exposed nanowires grown from the doped substrate regions and an insulator core with embedded nanowires. In a different aspect, the method forms a growth promotion layer overlying the substrate. The resultant structure includes exposed nanowires grown from the selectively formed growth promotion layer.

9. 发明授权

US07351995B2 Floating body germanium phototransistor having a photo absorption threshold bias region 有权
标题翻译：具有光吸收阈值偏置区域的浮体锗光电晶体管
公开(公告)号：US07351995B2
公开(公告)日：2008-04-01
申请号：US11894938
申请日：2007-08-22
申请人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
发明人： Sheng Teng Hsu , Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet
IPC分类号： H01L29/06 , H01L31/072 , H01L31/109 , H01L31/0328 , H01L31/062 , H01L31/113 , H01L31/0232
CPC分类号： H01L31/1136
摘要： A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.
摘要翻译：提出了具有光吸收阈值偏置区域的浮体锗（Ge）光电晶体管，以及相关的制造工艺。该方法包括：提供p掺杂硅（Si）衬底; 选择性地形成覆盖在所述Si衬底的第一表面上的绝缘体层; 形成覆盖绝缘体层的外延Ge层; 在Ge层中形成沟道区; 形成栅极电介质，栅电极和栅极间隔物; 在Ge层中形成源极/漏极（S / D）区域; 并且在Ge层中形成邻近沟道区的光吸收阈值偏置区域。在一个方面，第二S / D区域具有比第一S / D长度更长的长度。光吸收阈值偏置区域位于第二S / D区域的下方。或者，第二S / D区域与沟道分离偏移，光吸收阈值偏置区域是在光p掺杂之后的Ge层中的偏移。

10. 发明授权

US07233036B1 Double-junction filterless CMOS color imager cell 失效
标题翻译：双路无滤芯CMOS彩色成像单元
公开(公告)号：US07233036B1
公开(公告)日：2007-06-19
申请号：US11499081
申请日：2006-08-04
申请人： Sheng Teng Hsu , Jong-Jan Lee
发明人： Sheng Teng Hsu , Jong-Jan Lee
IPC分类号： H01L31/62 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/14603 , H01L27/14632 , H01L27/14645 , H01L27/14683 , H01L27/14689
摘要： A double-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cell is provided. The imager cell is fabricated from a silicon-on-insulator (SOI) substrate including a silicon (Si) substrate, a silicon dioxide insulator overlying the substrate, and a Si top layer overlying the insulator. A photodiode set is formed in the SOI substrate, including a first and second photodiode formed as a double-junction structure in the Si substrate. A third photodiode is formed in the Si top layer. A (imager sensing) transistor set is formed in the top Si layer. The transistor set is connected to the photodiode set and detects an independent output signal for each photodiode. The transistor set may be an eight-transistor (8T), a nine-transistor (9T), or an eleven-transistor (11T) cell.
摘要翻译：提供了一种双结互补金属氧化物半导体（CMOS）无滤色彩色成像单元。成像器单元由包括硅（Si）衬底，覆盖衬底的二氧化硅绝缘体和覆盖绝缘体的Si顶层的绝缘体上硅（SOI）衬底制造。在SOI衬底中形成光电二极管组，包括在Si衬底中形成为双结结构的第一和第二光电二极管。在Si顶层中形成第三光电二极管。在顶部Si层中形成A（成像器感测）晶体管组。晶体管组连接到光电二极管组，并检测每个光电二极管的独立输出信号。晶体管组可以是八晶体管（8T），九晶体管（9T）或十一晶体管（11T）单元。

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