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1. 发明授权

US08129279B2 Chemical mechanical polish process control for improvement in within-wafer thickness uniformity 有权
标题翻译：化学机械抛光过程控制，以提高晶片内厚度均匀性
公开(公告)号：US08129279B2
公开(公告)日：2012-03-06
申请号：US12250239
申请日：2008-10-13
申请人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
发明人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
IPC分类号： H01L21/302
CPC分类号： B24B37/013 , B24B49/12
摘要： A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.
摘要翻译：在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。根据厚度分布确定抛光配方。

2. 发明授权

US09132523B2 Chemical mechanical polish process control for improvement in within-wafer thickness uniformity 有权
标题翻译：化学机械抛光过程控制，以提高晶片内厚度均匀性
公开(公告)号：US09132523B2
公开(公告)日：2015-09-15
申请号：US13412260
申请日：2012-03-05
申请人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
发明人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
IPC分类号： H01L21/302 , B24B49/12 , B24B37/013
CPC分类号： B24B37/013 , B24B49/12
摘要： A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.
摘要翻译：在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。根据厚度分布确定抛光配方。

3. 发明申请

US20100093259A1 Chemical Mechanical Polish Process Control for Improvement in Within-Wafer Thickness Uniformity 有权
标题翻译：化学机械抛光过程控制，提高晶片内厚度均匀性
公开(公告)号：US20100093259A1
公开(公告)日：2010-04-15
申请号：US12250239
申请日：2008-10-13
申请人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
发明人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
IPC分类号： B24B49/04 , B24B49/12
CPC分类号： B24B37/013 , B24B49/12
摘要： A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.
摘要翻译：在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。根据厚度分布确定抛光配方。

4. 发明申请

US20120164918A1 Chemical Mechanical Polish Process Control for Improvement in Within-Wafer Thickness Uniformity 审中-公开
标题翻译：化学机械抛光过程控制，提高晶片内厚度均匀性
公开(公告)号：US20120164918A1
公开(公告)日：2012-06-28
申请号：US13412260
申请日：2012-03-05
申请人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
发明人： Shen-Nan Lee , Ying-Mei Lin , Yu-Jen Cheng , Keung Hui , Huan-Just Lin
IPC分类号： H01L21/302 , B24B49/12
CPC分类号： B24B37/013 , B24B49/12
摘要： A method of performing chemical mechanical polish (CMP) processes on a wafer includes providing the wafer; determining a thickness profile of a feature on a surface of the wafer; and, after the step of determining the thickness profile, performing a high-rate CMP process on the feature using a polish recipe to substantially achieve a within-wafer thickness uniformity of the feature. The polish recipe is determined based on the thickness profile.
摘要翻译：在晶片上进行化学机械抛光（CMP）工艺的方法包括提供晶片; 确定晶片表面上的特征的厚度分布; 并且在确定厚度分布的步骤之后，使用抛光配方对特征进行高速率CMP处理，以基本上实现特征的晶片内厚度均匀性。根据厚度分布确定抛光配方。

5. 发明申请

US20100048007A1 HIGH PLANARIZING METHOD FOR USE IN A GATE LAST PROCESS 有权
标题翻译：用于门窗最后过程的高平面化方法
公开(公告)号：US20100048007A1
公开(公告)日：2010-02-25
申请号：US12499439
申请日：2009-07-08
申请人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
发明人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/306 , H01L21/28
CPC分类号： B24B37/042 , H01L21/28079 , H01L21/31053 , H01L21/3212 , H01L21/823807 , H01L21/823828 , H01L29/66545 , H01L29/7843
摘要： A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.
摘要翻译：提供了一种用于进行化学机械抛光（CMP）的方法。该方法包括处理半导体衬底以在衬底上形成虚拟栅极结构，以在虚拟栅极结构上形成硬掩模，并在硬的基底上形成接触蚀刻停止层（CESL）和层间电介质（ILD）层用第一浆料进行第一CMP处理以修饰ILD层的非平面形貌，用第二浆料进行第二CMP处理以除去硬掩模，以及用第三浆料进行第三CMP处理以除去在半导体处理期间在虚拟栅极和硬掩模之间形成的界面层。

6. 发明授权

US08153526B2 High planarizing method for use in a gate last process 有权
标题翻译：用于门最后工艺的高平面化方法
公开(公告)号：US08153526B2
公开(公告)日：2012-04-10
申请号：US12499439
申请日：2009-07-08
申请人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
发明人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B24B37/042 , H01L21/28079 , H01L21/31053 , H01L21/3212 , H01L21/823807 , H01L21/823828 , H01L29/66545 , H01L29/7843
摘要： A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.
摘要翻译：提供了一种用于进行化学机械抛光（CMP）的方法。该方法包括处理半导体衬底以在衬底上形成虚拟栅极结构，以在虚拟栅极结构上形成硬掩模，并在硬的基底上形成接触蚀刻停止层（CESL）和层间电介质（ILD）层用第一浆料进行第一CMP处理以修饰ILD层的非平面形貌，用第二浆料进行第二CMP处理以除去硬掩模，以及用第三浆料进行第三CMP处理以除去在半导体处理期间在虚拟栅极和硬掩模之间形成的界面层。

7. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

8. 发明授权

US08222136B2 Method of forming contacts for a semiconductor device 有权
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US08222136B2
公开(公告)日：2012-07-17
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

9. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

10. 发明授权

US07023042B2 Method of forming a stacked capacitor structure with increased surface area for a DRAM device 有权
标题翻译：形成用于DRAM器件的具有增加的表面积的堆叠电容器结构的方法
公开(公告)号：US07023042B2
公开(公告)日：2006-04-04
申请号：US10755498
申请日：2004-01-12
申请人： Bor-Wen Chan , Huan-Just Lin , Hun-Jan Tao
发明人： Bor-Wen Chan , Huan-Just Lin , Hun-Jan Tao
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L28/88 , H01L27/10814 , H01L27/10852
摘要： A process for forming a DRAM stacked capacitor structure with increased surface area, has been developed. The process features forming lateral grooves in the sides of a polysilicon storage node structure, during a dry etching procedure used to define the storage node structure. The grooves are selectively, and laterally formed in ion implanted veins, which in turn had been placed at various depths in an intrinsic polysilicon layer via a series of ion implantation steps, each performed at a specific implant energy. An isotopic component of the storage node structure, defining dry etch procedure, selectively etches the highly doped, ion implanted veins at a greater rate than the non-ion implanted regions of polysificon, located between the ion implanted veins, resulting in a necked profile, storage node structure, featuring increased surface area as a result of the formation of the lateral grooves.
摘要翻译：已经开发了用于形成具有增加的表面积的DRAM叠层电容器结构的工艺。该工艺在用于限定存储节点结构的干蚀刻过程中，在多晶硅存储节点结构的侧面形成横向凹槽。这些凹槽是选择性地和侧向地形成在离子植入的静脉中，这些静脉又通过一系列离子注入步骤而被放置在本征多晶硅层中的各种深度处，每个离子注入步骤以特定的注入能量进行。存储节点结构的同位素组分定义了干蚀刻过程，选择性地以高于离子植入的静脉之间的聚合物的非离子注入区域的速率以更高的速率蚀刻高度掺杂的离子植入的静脉，产生颈缩轮廓，存储节点结构，由于形成横向槽而具有增加的表面积。

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