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1. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

2. 发明授权

US08048752B2 Spacer shape engineering for void-free gap-filling process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US08048752B2
公开(公告)日：2011-11-01
申请号：US12179395
申请日：2008-07-24
申请人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

3. 发明授权

US06541834B1 Silicon pressure micro-sensing device and the fabrication process 失效
标题翻译：硅压敏元件及其制造工艺
公开(公告)号：US06541834B1
公开(公告)日：2003-04-01
申请号：US09975125
申请日：2001-10-09
申请人： Jin-shown Shie , Ji-cheng Lin , Chun-te Lin , Chih-tang Peng , Shih-han Yu , Kuo-ning Chiang
发明人： Jin-shown Shie , Ji-cheng Lin , Chun-te Lin , Chih-tang Peng , Shih-han Yu , Kuo-ning Chiang
IPC分类号： H01L2982
CPC分类号： B81C1/00182 , B81B2201/0264 , B81B2203/0127 , B81B2203/0315 , B81C2201/014 , B81C2201/016 , G01L9/0054
摘要： The invention is a silicon pressure micro-sensing device and the fabrication process thereof. The silicon pressure micro-sensing device includes a pressure chamber, and is constituted of a P-type substrate with a taper chamber and an N-type epitaxial layer thereon. On the N-type epitaxial layer are a plurality of piezo-resistance sensing units which sense deformation caused by pressure. The fabrication pressure of the silicon pressure micro-sensing device includes a step of first making a plurality of holes on the N-type epitaxial layer to reach the P-type substrate beneath. Then, by an anisotropic etching stop technique, in which etchant pass through the holes, a taper chamber is formed in the P-type substrate. Finally, an insulating material is applied to seal the holes, thus attaining the silicon pressure micro-sensing device that is able to sense pressure differences between two ends thereof.
摘要翻译：本发明是一种硅压力微型感测装置及其制造方法。硅压力微型感测装置包括压力室，由具有锥形室的P型衬底和其上的N型外延层构成。在N型外延层上是感测由压力引起的变形的多个压电感测单元。硅压力微型感测装置的制造压力包括首先在N型外延层上制造多个孔以到达下面的P型衬底的步骤。然后，通过各向异性蚀刻停止技术，其中蚀刻剂穿过孔，在P型衬底中形成锥形室。最后，施加绝缘材料以密封孔，从而获得能够感测其两端之间的压力差的硅压力微检测装置。

4. 发明授权

US09647066B2 Dummy FinFET structure and method of making same 有权
公开(公告)号：US09647066B2
公开(公告)日：2017-05-09
申请号：US13454960
申请日：2012-04-24
申请人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
发明人： Chang-Shen Lu , Chih-Tang Peng , Tai-Chun Huang , Pei-Ren Jeng , Hao-Ming Lien , Yi-Hung Lin , Tze-Liang Lee , Syun-Ming Jang
IPC分类号： H01L27/088 , H01L29/10 , H01L21/8234 , H01L29/66 , H01L29/78 , H01L21/20
CPC分类号： H01L29/10 , H01L21/823431 , H01L27/0886 , H01L29/6681 , H01L29/785
摘要： A FinFET device may include a dummy FinFET structure laterally adjacent an active FinFET structure to reduce stress imbalance and the effects of stress imbalance on the active FinFET structure. The FinFET device comprises an active FinFET comprising a plurality of semiconductor fins, and a dummy FinFET comprising a plurality of semiconductor fins. The active FinFET and the dummy FinFET are laterally spaced from each other by a spacing that is related to the fin pitch of the active FinFET.

5. 发明授权

US09142402B2 Uniform shallow trench isolation regions and the method of forming the same 有权
标题翻译：均匀浅沟槽隔离区及其形成方法
公开(公告)号：US09142402B2
公开(公告)日：2015-09-22
申请号：US13307847
申请日：2011-11-30
申请人： Yu-Ling Liou , Chih-Tang Peng , Pei-Ren Jeng , Hao-Ming Lien , Tze-Liang Lee
发明人： Yu-Ling Liou , Chih-Tang Peng , Pei-Ren Jeng , Hao-Ming Lien , Tze-Liang Lee
IPC分类号： H01L21/425 , H01L21/02 , H01L21/762 , H01L21/8234 , H01L21/3115
CPC分类号： H01L21/76237 , H01L21/02164 , H01L21/02304 , H01L21/02315 , H01L21/31155 , H01L21/76224 , H01L21/823431 , H01L21/823481
摘要： A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively.
摘要翻译：一种方法包括同时对第一材料的第一表面和第二材料的第二表面进行等离子体处理，其中第一材料与第二材料不同。在第一材料的经处理的第一表面和第二材料的经处理的第二表面上形成第三材料。第一，第二和第三材料可以分别包括硬掩模，半导体材料和氧化物。

6. 发明授权

US08580653B2 Method for fabricating an isolation structure 有权
标题翻译：隔离结构的制造方法
公开(公告)号：US08580653B2
公开(公告)日：2013-11-12
申请号：US13775907
申请日：2013-02-25
申请人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
发明人： Tze-Liang Lee , Pei-Ren Jeng , Chu-Yun Fu , Chyi Shyuan Chern , Jui-Hei Huang , Chih-Tang Peng , Hao-Ming Lien
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L21/76232
摘要： A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
摘要翻译：一种制造隔离结构的方法，包括在衬底的顶表面中形成沟槽并用第一氧化物部分地填充沟槽，其中第一氧化物是纯氧化物。部分地填充沟槽包括在沟槽中形成衬层，并且在低于10毫托（mTorr）的压力和约500℃至约1000℃的温度下使用硅烷和氧前体在衬层上形成第一氧化物该方法还包括在第一氧化物的顶部产生固体反应产物。该方法还包括通过在室内在100℃至200℃的温度下加热基底来升华固体反应产物，并通过使载气流过基底而除去升华的固体反应产物。该方法还包括用第二氧化物填充沟槽。

7. 发明授权

US08546891B2 Fin profile structure and method of making same 有权
标题翻译：翅片轮廓结构及其制作方法
公开(公告)号：US08546891B2
公开(公告)日：2013-10-01
申请号：US13408538
申请日：2012-02-29
申请人： Chia-Wei Chang , Chih-Fang Liu , Chih-Tang Peng , Tai-Chun Huang , Ryan Chia-Jen Chen
发明人： Chia-Wei Chang , Chih-Fang Liu , Chih-Tang Peng , Tai-Chun Huang , Ryan Chia-Jen Chen
IPC分类号： H01L29/78
CPC分类号： H01L21/3065 , H01L29/06 , H01L29/66795 , H01L29/7853
摘要： A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin.
摘要翻译： FinFET器件可以包括横向邻近第二半导体鳍片的第一半导体鳍片。第一半导体鳍片和第二半导体鳍片可以具有最小化缺陷和变形的轮廓。第一半导体鳍片包括上部和下部。第一半导体鳍片的下部可以具有在底部比第一半导体鳍片的上部更宽的扩张轮廓。第二半导体散热片包括上部和下部。第二半导体鳍片的下部可以具有比第二半导体鳍片的上部更宽但小于第一半导体鳍片的下部的扩口形状。

8. 发明申请

US20120025329A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20120025329A1
公开(公告)日：2012-02-02
申请号：US13270585
申请日：2011-10-11
申请人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuah Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

9. 发明授权

US08736016B2 Strained isolation regions 有权
标题翻译：应变隔离区
公开(公告)号：US08736016B2
公开(公告)日：2014-05-27
申请号：US11759791
申请日：2007-06-07
申请人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
发明人： Mong-Song Liang , Tze-Liang Lee , Kuo-Tai Huang , Chao-Cheng Chen , Hao-Ming Lien , Chih-Tang Peng
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/76224 , H01L29/7833 , H01L29/7843 , H01L29/7846
摘要： An isolation trench having localized stressors is provided. In accordance with embodiments of the present invention, a trench is formed in a substrate and partially filled with a dielectric material. In an embodiment, the trench is filled with a dielectric layer and a planarization step is performed to planarize the surface with the surface of the substrate. The dielectric material is then recessed below the surface of the substrate. In the recessed portion of the trench, the dielectric material may remain along the sidewalls or the dielectric material may be removed along the sidewalls. A stress film, either tensile or compressive, may then be formed over the dielectric material within the recessed portion. The stress film may also extend over a transistor or other semiconductor structure.
摘要翻译：提供了具有局部应力源的隔离沟槽。根据本发明的实施例，在衬底中形成沟槽并且部分地填充有电介质材料。在一个实施例中，沟槽被填充有电介质层，并且执行平面化步骤以使其与衬底的表面平坦化。然后将电介质材料凹入到衬底的表面下方。在沟槽的凹陷部分中，电介质材料可以沿着侧壁保留，或者电介质材料可以沿侧壁去除。然后可以在凹陷部分内的电介质材料上形成拉伸或压缩的应力膜。应力膜也可以在晶体管或其它半导体结构上延伸。

10. 发明申请

US20130330906A1 METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：半导体集成电路制造方法
公开(公告)号：US20130330906A1
公开(公告)日：2013-12-12
申请号：US13490635
申请日：2012-06-07
申请人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
发明人： Weibo Yu , Ming-His Yeh , Chih-Tang Peng , Hao-Ming Lien , Chao-Cheng Chen , Syun-Ming Jang
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L29/66795
摘要： A method of fabricating a semiconductor IC is disclosed. The method includes receiving a device. The device includes a semiconductor substrate, a plurality of fins and trenches between fins in the semiconductor substrate. The method also includes filling the trenches with a dielectric material to form shallow trench isolations (STI), applying a low-thermal-budget annealing to the dielectric material, and applying a wet-treatment to the dielectric material.
摘要翻译：公开了制造半导体IC的方法。该方法包括接收设备。该器件包括半导体衬底，半导体衬底中的翅片之间的多个散热片和沟槽。该方法还包括用介电材料填充沟槽以形成浅沟槽隔离（STI），对介电材料施加低热预算退火，以及对电介质材料进行湿法处理。

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