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1. 发明授权

US08222136B2 Method of forming contacts for a semiconductor device 有权
标题翻译：形成半导体器件的触点的方法
公开(公告)号：US08222136B2
公开(公告)日：2012-07-17
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

2. 发明申请

US20120094485A1 METHOD OF FORMING CONTACTS FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件接触的方法
公开(公告)号：US20120094485A1
公开(公告)日：2012-04-19
申请号：US12906868
申请日：2010-10-18
申请人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
发明人： Yuan-Tien Tu , Tsai-Chun Li , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/28
CPC分类号： H01L21/76814 , H01L21/02063 , H01L21/76816
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成层。所述方法包括在所述层中形成暴露所述衬底的第一区域的第一开口。该方法包括通过第一溅射工艺去除在第一区域上形成的第一氧化层。该方法包括用导电材料填充第一开口。所述方法包括在所述层中形成暴露所述衬底的第二区域的第二开口，所述第二区域不同于所述第一区域。该方法包括通过第二溅射工艺除去在第二区域上形成的第二氧化层。第一和第二溅射工艺之一比另一个更强大。

3. 发明申请

US20130056837A1 SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：用于高K金属栅极设备的自对准绝缘膜
公开(公告)号：US20130056837A1
公开(公告)日：2013-03-07
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L29/772 , H01L21/336 , H01L21/28
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

4. 发明授权

US08822283B2 Self-aligned insulated film for high-k metal gate device 有权
标题翻译：用于高k金属栅极器件的自对准绝缘膜
公开(公告)号：US08822283B2
公开(公告)日：2014-09-02
申请号：US13244365
申请日：2011-09-24
申请人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
发明人： Jin-Aun Ng , Maxi Chang , Jen-Sheng Yang , Ta-Wei Lin , Shih-Hao Lo , Chih-Yang Yeh , Hui-Wen Lin , Jung-Hui Kao , Yuan-Tien Tu , Huan-Just Lin , Chih-Tang Peng , Pei-Ren Jeng , Bao-Ru Young , Hak-Lay Chuang
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/66
CPC分类号： H01L21/28229 , H01L21/28079 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/42364 , H01L29/4958 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6659
摘要： A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure.
摘要翻译：制造集成电路的方法包括提供半导体衬底并在诸如高k电介质的衬底上形成栅极电介质。在半导体衬底上形成金属栅极结构，并在其上形成一个薄的电介质膜。薄介电膜包括从金属栅极与金属组合的氮氧化合物。该方法还包括在金属栅极结构的两侧提供层间电介质（ILD）。

5. 发明授权

US08546227B2 Contact for high-K metal gate device 有权
标题翻译：高K金属门装置的接触
公开(公告)号：US08546227B2
公开(公告)日：2013-10-01
申请号：US13289112
申请日：2011-11-04
申请人： Hak-Lay Chuang , Sheng-Chen Chung , Wei Cheng Wu , Bao-Ru Young , Huan-Just Lin , Tsai-Chun Li
发明人： Hak-Lay Chuang , Sheng-Chen Chung , Wei Cheng Wu , Bao-Ru Young , Huan-Just Lin , Tsai-Chun Li
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L29/78 , H01L21/28114 , H01L21/76805 , H01L21/76816 , H01L21/823842 , H01L29/41775 , H01L29/42376 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.
摘要翻译：制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。然后用导电材料填充沟槽和底切。

6. 发明申请

US20130069174A1 CONTACT FOR HIGH-K METAL GATE DEVICE 有权
标题翻译：联系高K金属门装置
公开(公告)号：US20130069174A1
公开(公告)日：2013-03-21
申请号：US13289112
申请日：2011-11-04
申请人： Hak-Lay Chuang , Sheng-Chen Chung , Wei Cheng Wu , Bao-Ru Young , Huan-Just Lin , Tsai-Chun Li
发明人： Hak-Lay Chuang , Sheng-Chen Chung , Wei Cheng Wu , Bao-Ru Young , Huan-Just Lin , Tsai-Chun Li
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/78 , H01L21/28114 , H01L21/76805 , H01L21/76816 , H01L21/823842 , H01L29/41775 , H01L29/42376 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.
摘要翻译：制造集成电路的方法包括：提供具有高k电介质的衬底并在高k电介质上提供多晶硅栅极结构。在与多晶硅栅极结构相邻的衬底上执行掺杂工艺，之后去除多晶硅栅极结构并用金属栅极结构代替。在金属栅极结构和掺杂衬底上沉积层间电介质（ILD），并且干蚀刻工艺在ILD中形成到金属栅极结构的顶表面的沟槽。在干蚀刻工艺之后，湿蚀刻工艺在金属栅极结构的顶表面附近形成底切。然后用导电材料填充沟槽和底切。

7. 发明授权

US07157350B2 Method of forming SOI-like structure in a bulk semiconductor substrate using self-organized atomic migration 有权
公开(公告)号：US07157350B2
公开(公告)日：2007-01-02
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/76
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.

8. 发明申请

US20050253194A1 SOI-like structure in a bulk semiconductor substrate and method of forming same 有权
标题翻译：体半导体衬底中的SOI类结构及其形成方法
公开(公告)号：US20050253194A1
公开(公告)日：2005-11-17
申请号：US10847607
申请日：2004-05-17
申请人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
发明人： Ji-Yi Yang , Chien-Hao Chen , Tze-Liang Lee , Shih-Chang Chen , Huan-Just Lin
IPC分类号： H01L21/324 , H01L21/762 , H01L27/01 , H01L27/12
CPC分类号： H01L21/3247 , H01L21/76232 , H01L21/76283 , H01L27/1203
摘要： Bulk silicon is transformed into an SOI-like structure by annealing. Trenches are formed in a bulk substrate to define device sites. The lower portions of the trenches are annealed at low pressure in a hydrogen atmosphere. This transforms the lower trench portions to expanded, spheroidal voids that extend under the device sites. Neighboring voids each reside about half way under an intervening site. A silicon-consuming process forms a liner on the walls of the voids, with the liners on neighboring voids abutting to isolate the intervening device site from the substrate and other device sites.
摘要翻译：通过退火将体硅转变成SOI样结构。沟槽形成在大量衬底中以限定器件位置。沟槽的下部在氢气气氛中在低压下退火。这将下沟槽部分转变成在器件位置下延伸的膨胀的球状空隙。相邻的空洞每个居住在中间位置的一半左右。消耗硅的过程在空隙的壁上形成衬垫，相邻空隙上的衬垫邻接以将介入的器件位置与衬底和其它器件位置隔离。

9. 发明申请

US20100048007A1 HIGH PLANARIZING METHOD FOR USE IN A GATE LAST PROCESS 有权
标题翻译：用于门窗最后过程的高平面化方法
公开(公告)号：US20100048007A1
公开(公告)日：2010-02-25
申请号：US12499439
申请日：2009-07-08
申请人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
发明人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/306 , H01L21/28
CPC分类号： B24B37/042 , H01L21/28079 , H01L21/31053 , H01L21/3212 , H01L21/823807 , H01L21/823828 , H01L29/66545 , H01L29/7843
摘要： A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.
摘要翻译：提供了一种用于进行化学机械抛光（CMP）的方法。该方法包括处理半导体衬底以在衬底上形成虚拟栅极结构，以在虚拟栅极结构上形成硬掩模，并在硬的基底上形成接触蚀刻停止层（CESL）和层间电介质（ILD）层用第一浆料进行第一CMP处理以修饰ILD层的非平面形貌，用第二浆料进行第二CMP处理以除去硬掩模，以及用第三浆料进行第三CMP处理以除去在半导体处理期间在虚拟栅极和硬掩模之间形成的界面层。

10. 发明授权

US08153526B2 High planarizing method for use in a gate last process 有权
标题翻译：用于门最后工艺的高平面化方法
公开(公告)号：US08153526B2
公开(公告)日：2012-04-10
申请号：US12499439
申请日：2009-07-08
申请人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
发明人： Shen-Nan Lee , Huan-Just Lin , Shih-Chang Chen
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B24B37/042 , H01L21/28079 , H01L21/31053 , H01L21/3212 , H01L21/823807 , H01L21/823828 , H01L29/66545 , H01L29/7843
摘要： A method for performing a chemical-mechanical polishing (CMP) is provided. The method includes processing a semiconductor substrate to form a dummy gate structure on the substrate, to form a hard mask on the dummy gate structure, and to form a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer on the hard mask, performing a first CMP process with a first slurry to modify a non-planar topography of the ILD layer, performing a second CMP process with a second slurry to remove the hard mask, and performing a third CMP process with a third slurry to remove an interfacial layer that forms between the dummy gate and hard mask during semiconductor processing.
摘要翻译：提供了一种用于进行化学机械抛光（CMP）的方法。该方法包括处理半导体衬底以在衬底上形成虚拟栅极结构，以在虚拟栅极结构上形成硬掩模，并在硬的基底上形成接触蚀刻停止层（CESL）和层间电介质（ILD）层用第一浆料进行第一CMP处理以修饰ILD层的非平面形貌，用第二浆料进行第二CMP处理以除去硬掩模，以及用第三浆料进行第三CMP处理以除去在半导体处理期间在虚拟栅极和硬掩模之间形成的界面层。

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