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1. 发明申请

US20070102812A1 Reduction of macro level stresses in copper/Low-K wafers by altering aluminum pad/passivation stack to reduce or eliminate IMC cracking in post wire bonded dies 有权
标题翻译：通过改变铝焊盘/钝化层来减少或消除后线焊接模具中的IMC裂纹来减少铜/低K晶片中的宏观水平应力
公开(公告)号：US20070102812A1
公开(公告)日：2007-05-10
申请号：US11269275
申请日：2005-11-08
申请人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
发明人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05124 , H01L2224/05147 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/48824 , H01L2224/48844 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 μm. Another possibility is provide an extra 0.6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 μm aluminum layer, followed by another barrier layer of 60 nm, another aluminum layer of 0.6 μm and another barrier layer of 60 nm.
摘要翻译：一种衬垫结构和钝化方案，可在Cu / Low-K BEOL处理期间减少或消除后引线键合模具中的IMC裂纹。可以在1.2μm铝层和铜之间提供厚120nm的阻挡层。另一种可能性是有效地分离阻挡层，其中铝层设置在两个阻挡层之间。阻挡层可以是60nm，而设置在阻挡层之间的铝层可以是0.6μm。另一种可能性是在顶部阻挡层上提供额外的0.6μm的铝层。另一种可能性是在最顶层的铝层上提供额外的阻挡层，使得在0.6μm的铝层上提供60nm的顶部阻挡层，接着是60nm的另一阻挡层，另一个为0.6的铝层妈妈和60nm的另一阻挡层。

2. 发明授权

US08076779B2 Reduction of macro level stresses in copper/low-K wafers 有权
标题翻译：降低铜/低K晶片的宏观水平应力
公开(公告)号：US08076779B2
公开(公告)日：2011-12-13
申请号：US11269275
申请日：2005-11-08
申请人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
发明人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05124 , H01L2224/05147 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/48824 , H01L2224/48844 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 μm. Another possibility is provide an extra 0.6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 μm aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 μm and another barrier layer of 60 nm.
摘要翻译：一种衬垫结构和钝化方案，可在Cu / Low-k BEOL处理期间减少或消除后引线键合模具中的IMC裂纹。可以在1.2μm的铝层和铜之间设置厚120nm的阻挡层。另一种可能性是有效地分离阻挡层，其中铝层设置在两个阻挡层之间。阻挡层可以是60nm，而设置在阻挡层之间的铝层可以是0.6μm。另一种可能性是在顶部阻挡层上提供额外的0.6μm的铝层。另一种可能性是在最顶层的铝层上提供额外的阻挡层，使得在0.6μm的铝层上设置60nm的顶部阻挡层，接着是60nm的另一个阻挡层，另一个为0.6的铝层 μm，另一个阻挡层为60nm。

3. 发明申请

US20070123024A1 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing 失效
标题翻译：消除后引线键合芯片中的IMC裂纹：在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
公开(公告)号：US20070123024A1
公开(公告)日：2007-05-31
申请号：US11290087
申请日：2005-11-30
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48724 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
摘要翻译：减少或消除引线接合部件中的IMC裂纹问题的不同方法，包括：改变为顶部R 1和R 2的更多的压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

4. 发明授权

US07531442B2 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing 失效
标题翻译：消除后引线键合芯片中的IMC裂纹：在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
公开(公告)号：US07531442B2
公开(公告)日：2009-05-12
申请号：US11290087
申请日：2005-11-30
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
IPC分类号： H01L21/44
CPC分类号： H01L21/76801 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48724 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
摘要翻译：减少或消除电线接合部件中IMC裂纹问题的不同方式，包括：更换为顶部，R1和R2的更多压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

5. 发明申请

US20060281256A1 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US20060281256A1
公开(公告)日：2006-12-14
申请号：US11312849
申请日：2005-12-20
申请人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

6. 发明申请

US20060278902A1 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US20060278902A1
公开(公告)日：2006-12-14
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
发明人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

7. 发明申请

US20070259518A1 Method and apparatus for diverting void diffusion in integrated circuit conductors 有权
标题翻译：用于在集成电路导体中转移空穴扩散的方法和装置
公开(公告)号：US20070259518A1
公开(公告)日：2007-11-08
申请号：US11323398
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L29/06 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/7682 , H01L21/76808 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.
摘要翻译：在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

8. 发明申请

US20070155160A1 Method and apparatus for redirecting void diffusion away from vias in an integrated circuit design 有权
标题翻译：在集成电路设计中将空隙扩散远离过孔的方法和装置
公开(公告)号：US20070155160A1
公开(公告)日：2007-07-05
申请号：US11323400
申请日：2005-12-29
申请人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
发明人： Derryl Allman , Hemanshu Bhatt , Charles May , Peter Burke , Byung-Sung Kwak , Sey-Shing Sun , David Price , David Pritchard
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L24/02 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/14
摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.
摘要翻译：用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

9. 发明授权

US07179736B2 Method for fabricating planar semiconductor wafers 有权
标题翻译：制造平面半导体晶圆的方法
公开(公告)号：US07179736B2
公开(公告)日：2007-02-20
申请号：US10966074
申请日：2004-10-14
申请人： Byung-Sung Leo Kwak , Peter Burke , Sey-Shing Sun
发明人： Byung-Sung Leo Kwak , Peter Burke , Sey-Shing Sun
IPC分类号： H01L21/4763
CPC分类号： H01L21/76877 , C25D5/18 , C25D7/123 , H01L21/2885 , H01L21/7684
摘要： The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration. Over-plating on the wafer in the areas of the vias and trenches is therefore avoided, resulting in a more planar metallization layer on the wafer, without the use of a leveler additive which adversely affects the gapfill capability.
摘要翻译：本发明涉及一种制造平面半导体晶片的方法。该方法包括在半导体晶片表面上形成电介质层，该半导体晶片表面具有通孔，沟槽和平面区域。然后在电介质层上形成阻挡层和种子金属层。晶片是包含加速器的镀液中的下一个位置，该加速器倾向于在通路和沟槽中收集，以加速相对于晶片的平面区域在这些区域中的电镀速率。达到间隙填充点后，通过去除晶片上的电镀偏压来停止电镀。然后在该过程中引入平衡时段，允许较高浓度的促进剂添加剂和浴中的其它组分）]在通孔和沟槽区域上方在电镀浴中平衡。平衡后恢复晶片上的块体电镀。因此避免了在通孔和沟槽区域上的晶片上的过电镀，导致晶片上更平面的金属化层，而不使用不利地影响间隙填充能力的矫直添加剂。

10. 发明申请

US20060063375A1 Integrated barrier and seed layer for copper interconnect technology 有权
标题翻译：铜互连技术的集成屏障和种子层
公开(公告)号：US20060063375A1
公开(公告)日：2006-03-23
申请号：US10945777
申请日：2004-09-20
申请人： Sey-Shing Sun , Byung-Sung Kwak , Peter Burke
发明人： Sey-Shing Sun , Byung-Sung Kwak , Peter Burke
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76843 , H01L21/76846 , H01L21/76871 , H01L21/76873 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An integrated barrier and seed layer that is useful for creating conductive pathways in semiconductor devices. The barrier portion of the integrated layer prevents diffusion of the conductive material into the underlying dielectric substrate while the seed portion provides an appropriate foundation upon which to deposit the conductive material. The barrier portion of the integrated layer is formed of a metal nitride, while the seed portion is formed of ruthenium or a ruthenium alloy. The metal nitride forms an effective barrier layer while the ruthenium or ruthenium alloy forms an effective seed layer for a metal such as copper. In some embodiments, the integrated layer is formed in a way so that its composition changes gradually from one region to the next.
摘要翻译：集成的屏障和种子层，可用于在半导体器件中产生导电通路。集成层的阻挡部分防止导电材料扩散到下面的电介质基底中，同时种子部分提供了沉积导电材料的适当基础。集成层的阻挡部分由金属氮化物形成，而种子部分由钌或钌合金形成。金属氮化物形成有效的阻挡层，而钌或钌合金形成金属如铜的有效晶种层。在一些实施例中，集成层以使其组成从一个区域逐渐变化到下一个区域的方式形成。

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