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1. 发明授权

US08384165B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US08384165B2
公开(公告)日：2013-02-26
申请号：US12140773
申请日：2008-06-17
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L29/49 , H01L29/51
CPC分类号： H01L29/49 , G02B6/3897 , G02B6/445 , H01L29/51 , H02G15/117
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

2. 发明授权

US07312127B2 Incorporating dopants to enhance the dielectric properties of metal silicates 有权
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US07312127B2
公开(公告)日：2007-12-25
申请号：US11389643
申请日：2006-03-23
申请人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763 , B05D3/02
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含III族金属。

3. 发明授权

US07189628B1 Fabrication of trenches with multiple depths on the same substrate 有权
标题翻译：在同一基板上制作具有多个深度的沟槽
公开(公告)号：US07189628B1
公开(公告)日：2007-03-13
申请号：US10931605
申请日：2004-08-31
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/461
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译：通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。浅沟和深沟的蚀刻然后同时进行。

4. 发明申请

US20050127458A1 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US20050127458A1
公开(公告)日：2005-06-16
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/3115 , H01L21/316 , H01L29/76
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含IV族金属。

5. 发明申请

US20060281256A1 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US20060281256A1
公开(公告)日：2006-12-14
申请号：US11312849
申请日：2005-12-20
申请人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

6. 发明授权

US06355532B1 Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET 有权
标题翻译：制造短路和垂直取向通道，双栅极，CMOS FET的减法氧化法
公开(公告)号：US06355532B1
公开(公告)日：2002-03-12
申请号：US09413667
申请日：1999-10-06
申请人： John J. Seliskar , Verne Hornback , David Daniel
发明人： John J. Seliskar , Verne Hornback , David Daniel
IPC分类号： H01L21336
CPC分类号： H01L29/7851 , B82Y10/00 , H01L21/823807 , H01L21/82385 , H01L27/092 , H01L29/4236 , H01L29/66439 , H01L29/66621 , H01L29/66795 , H01L29/775 , H01L29/78 , H01L29/7854
摘要： A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically. The relatively narrow channel widths allow fully-depleted and fully-inverted conductivity characteristics which enhance the conductivity characteristics of the FET despite its reduced size, without silicon on insulator (SOI) constructions or epitaxial substrates.
摘要翻译：通过在源极和漏极区域之间纵向延伸的起始材料中形成多个通道段来制造短垂直通道双栅极CMOS FET。通道段通过空间横向分开，并且优选地由位于空间之间的起始材料的柱形成。柱被横向氧化并且去除氧化以减小柱的宽度并形成通道段。在通道段之间的空间中形成栅极结构。每个柱的宽度由常规的同时期的光刻曝光和蚀刻限定，但是每个通道段的宽度基本上小于光刻产生的耐蚀刻屏障的宽度。相对窄的沟道宽度允许完全耗尽和完全反转的导电特性，尽管其尺寸减小，但是绝缘体上硅（SOI）构造或外延衬底，其增强了FET的导电特性。

7. 发明授权

US6071562A Process for depositing titanium nitride films 失效
标题翻译：氮化钛膜沉积工艺
公开(公告)号：US6071562A
公开(公告)日：2000-06-06
申请号：US74298
申请日：1998-05-07
申请人： Verne Hornback , Derryl Allman
发明人： Verne Hornback , Derryl Allman
IPC分类号： C23C16/34
CPC分类号： C23C16/34
摘要： The present invention provides an efficient process for depositing a titanium nitride film on a substrate. The process comprises the steps of heating the substrate and subsequently exposing the heated substrate to a first gas containing tetrakis(dimethylamido)titanium and to a second gas containing tetrakis(diethylamido)titanium.
摘要翻译：本发明提供了一种在衬底上沉积氮化钛膜的有效方法。该方法包括加热基底并随后将加热的基底暴露于含有四（二甲基氨基）钛的第一气体和含有四（二乙基氨基）钛的第二气体的步骤。

8. 发明授权

US07405116B2 Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow 有权
标题翻译：门边缘衬垫的应用以保持栅极长度CD在替代栅极晶体管流中
公开(公告)号：US07405116B2
公开(公告)日：2008-07-29
申请号：US10916322
申请日：2004-08-11
申请人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
发明人： Richard J. Carter , Wai Lo , Sey-Shing Sun , Hong Lin , Verne Hornback
IPC分类号： H01L21/338
CPC分类号： H01L29/6656 , H01L21/823828 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.
摘要翻译：保持良好限定的栅极堆叠轮廓的方法，沉积或生长均匀的栅极电介质，并且通过在虚拟栅极蚀刻之后和间隔物工艺之前沉积的惰性绝缘衬垫来维持栅极长度CD控制。衬垫材料对用于去除伪栅极氧化物的湿化学品是选择性的，从而防止间隔区域中的底切。该方法旨在使金属栅极电极技术成为与现有制造环境兼容的可行技术，用于多代CMOS晶体管，包括属于65nm，45nm和25nm技术节点的CMOS晶体管，这些晶体管正在用于模拟，数字或混合信号集成电路，用于通信，娱乐，教育和安全产品等各种应用。

9. 发明授权

US07064062B2 Incorporating dopants to enhance the dielectric properties of metal silicates 失效
标题翻译：掺入掺杂剂以增强金属硅酸盐的介电性能
公开(公告)号：US07064062B2
公开(公告)日：2006-06-20
申请号：US10738761
申请日：2003-12-16
申请人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
发明人： Wai Lo , Verne Hornback , Wilbur G. Catabay , Wei-Jen Hsia , Sey-Shing Sun
IPC分类号： H01L21/4763 , B05D3/02
CPC分类号： H01L21/02142 , H01L21/02323 , H01L21/3115 , H01L21/31604 , H01L21/31612 , H01L21/31637 , H01L21/31645
摘要： The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
摘要翻译：本发明提供了在半导体晶片上形成高k电介质层的方法。金属硅酸盐介电层最初沉积在晶片上。将具有可离解氧的掺杂剂引入到晶片上的金属硅酸盐中。根据一个实施方案，金属硅酸盐包含IV族金属，掺杂剂是碱金属和碱土金属之一的氧化物。根据另一个实施方案，金属硅酸盐包含III族金属。

10. 发明授权

US06864152B1 Fabrication of trenches with multiple depths on the same substrate 有权
标题翻译：在同一基板上制作具有多个深度的沟槽
公开(公告)号：US06864152B1
公开(公告)日：2005-03-08
申请号：US10442533
申请日：2003-05-20
申请人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
发明人： Mohammad R. Mirbedini , Venkatesh P. Gopinath , Hong Lin , Verne Hornback , Dodd Defibaugh , Ynhi Le
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/76229 , H01L21/76283
摘要： Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.
摘要翻译：通过形成具有对应于浅沟槽和深沟槽的最终深度的差的深度的初始沟槽，在同一晶片上实现双沟槽深度。第二个掩模用于打开初步沟槽上的深沟槽的区域，并在另外的位置打开浅沟槽。浅沟和深沟的蚀刻然后同时进行。

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