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1. 发明授权

US06340827B1 Diffusion barrier for use with high dielectric constant materials and electronic devices incorporating same 有权
标题翻译：用于高介电常数材料的扩散阻挡层和结合其的电子器件
公开(公告)号：US06340827B1
公开(公告)日：2002-01-22
申请号：US09478647
申请日：2000-01-06
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L3300
CPC分类号： H01L28/40 , H01L21/28568
摘要： A diffusion barrier for preventing the diffusion of oxygen from a high dielectric constant material to a titanium nitride layer. The diffusion barrier comprises one or more layers, wherein each of the one or more layers comprises a material selected from the group consisting of metal carbide, metal nitride, metal boride, metal carbo-nitride, and silicon carbide. The high dielectric constant material may be tantalum pentoxide or any perkovskite-type high dielectric constant material.
摘要翻译：用于防止氧从高介电常数材料扩散到氮化钛层的扩散屏障。扩散阻挡层包括一层或多层，其中一层或多层中的每层包括选自金属碳化物，金属氮化物，金属硼化物，金属碳氮化物和碳化硅的材料。高介电常数材料可以是五氧化二钽或任何一种钙钛矿型高介电常数材料。

2. 发明授权

US06168991A DRAM capacitor including Cu plug and Ta barrier and method of forming 有权
标题翻译：包括Cu插头和Ta阻挡层的DRAM电容器及其形成方法
公开(公告)号：US06168991A
公开(公告)日：2001-01-02
申请号：US09340062
申请日：1999-06-25
申请人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
发明人： Seungmoo Choi , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/76895 , H01L27/10852 , H01L27/10888 , H01L28/55 , H01L28/75
摘要： A capacitor for a DRAM cell comprises a first electrode layer, a second electrode layer, and a dielectric film. The capacitor is disposed in a first opening defined in a second dielectric layer and overlaying a first plug through a first dielectric layer. The first plug is electrically connected to a transistor. The first electrode layer is electrically connected to the first plug. The second electrode layer can act as a barrier between a second plug exposed by a second opening and the second opening. The first and second electrode layer can be formed from Ta and TaN, and the dielectric film can be formed from tantalum oxide. A plug layer electrically connected to the second electrode layer can also be included. The plug layer can be formed from copper. A method of forming the DRAM capacitor is also disclosed.
摘要翻译：用于DRAM单元的电容器包括第一电极层，第二电极层和电介质膜。电容器设置在限定在第二电介质层中的第一开口中，并且通过第一介电层覆盖第一插塞。第一插头电连接到晶体管。第一电极层电连接到第一插头。第二电极层可以用作由第二开口暴露的第二插头和第二开口之间的屏障。第一和第二电极层可以由Ta和TaN形成，并且电介质膜可以由氧化钽形成。电连接到第二电极层的插塞层也可以包括在内。插塞层可以由铜形成。还公开了形成DRAM电容器的方法。

3. 发明授权

US06313021B1 PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance 有权
标题翻译： PMOS器件具有用于改善硅化物完整性和增强的硼渗透电阻的层状硅栅极
公开(公告)号：US06313021B1
公开(公告)日：2001-11-06
申请号：US09416491
申请日：1999-10-12
申请人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
发明人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L213205
CPC分类号： H01L21/28035 , H01L21/28044 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4933 , H01L29/4941
摘要： The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.
摘要翻译：本发明提供了一种在半导体衬底上形成亚微米p型金属氧化物半导体（PMOS）结构的方法。该工艺包括在半导体衬底上形成栅极氧化物，通过以第一沉积速率沉积栅极氧化物上的第一栅极层，以栅极氧化物形成栅极层，并以第二沉积速率在第一层上沉积第二栅极层以在门结构内提供改进的应力调节。该工艺还包括在栅极上形成硅化物掺杂剂阻挡层。由于在栅极中存在改善的应力调节，硅化物掺杂剂势垒的完整性显着增强。这种增加的硅化物完整性防止在随后的制造工艺期间对硅化物掺杂剂阻挡层的显着损坏。因此，在形成与栅极结构相邻的源极和漏极区域期间，掺杂物势垒能够提供对掺杂剂穿透（例如硼）的预期程度的阻抗。

4. 发明授权

US5523259A Method of forming metal layers formed as a composite of sub-layers using Ti texture control layer 失效
标题翻译：使用Ti纹理控制层形成作为子层的复合物的金属层的方法
公开(公告)号：US5523259A
公开(公告)日：1996-06-04
申请号：US349649
申请日：1994-12-05
申请人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
发明人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5329 , H01L23/5226 , H01L2924/0002
摘要： In an integrated circuit, an opening (e.g., via or window) is filled with an Al-based plug which has essentially a orientation and comprises at most three grains. These characteristics are achieved by first depositing a texture control Ti layer having substantially a (002) basal plane orientation followed by at least three Al-based sublayers. The grain sizes and deposition conditions are controlled in such a way that during deposition of the third sublayer, the microstructure of the plug adjusts itself to produce a single grain (or at most three).
摘要翻译：在集成电路中，开口（例如，通孔或窗口）填充有基本上为111°取向且至多包含三个晶粒的Al-基塞。这些特性通过首先沉积具有基本上（002）基面平面取向的纹理控制Ti层，然后是至少三个基于Al的子层来实现。晶粒尺寸和沉积条件被控制为在沉积第三子层期间，插塞的微观结构自身调整以产生单个颗粒（或至多三个）。

5. 发明授权

US06323078B1 Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby 有权
标题翻译：使用多步快速热处理形成金属氧化物金属电容器的方法和由此形成的器件
公开(公告)号：US06323078B1
公开(公告)日：2001-11-27
申请号：US09418106
申请日：1999-10-14
申请人： Siddhartha Bhowmik , Sailesh M. Merchant , Pradip K. Roy , Sidhartha Sen
发明人： Siddhartha Bhowmik , Sailesh M. Merchant , Pradip K. Roy , Sidhartha Sen
IPC分类号： H01L218234
CPC分类号： H01L28/40
摘要： The present invention provides a method of forming a metal oxide metal (MOM) capacitor on a substrate, such as a silicon substrate, of a semiconductor wafer in a rapid thermal process (RTP) machine. The MOM capacitor is fabricated by forming a metal layer on the semiconductor substrate. The metal layer is then subjected to a first rapid thermal process in a substantially inert but nitrogen-free atmosphere that consumes a portion of the metal layer to form a first metal electrode layer and a silicide layer between the first metal electrode and the semiconductor substrate. The semiconductor wafer is then subjected to a second rapid thermal process. During this process, the remaining portion of the metal layer is oxidized to form a metal oxide on the first metal electrode, which serves as the dielectric layer of the MOM capacitor. Following the formation of the dielectric layer, a second metal electrode layer is then conventionally formed on the metal oxide, which completes the formation of the MOM capacitor. Preferably, the first electrode layer and the metal oxide layer are formed in a single RTP machine.
摘要翻译：本发明提供了一种在快速热处理（RTP）机器中在半导体晶片的衬底（例如硅衬底）上形成金属氧化物金属（MOM）电容器的方法。通过在半导体衬底上形成金属层来制造MOM电容器。然后在基本惰性但无氮的气氛中对金属层进行第一快速热处理，其消耗金属层的一部分以在第一金属电极和半导体衬底之间形成第一金属电极层和硅化物层。然后对半导体晶片进行第二快速热处理。在该过程中，金属层的剩余部分被氧化，在作为MOM电容器的电介质层的第一金属电极上形成金属氧化物。在形成电介质层之后，通常在金属氧化物上形成第二金属电极层，从而完成MOM电容器的形成。优选地，第一电极层和金属氧化物层在单个RTP机器中形成。

6. 发明授权

US5489552A Multiple layer tungsten deposition process 失效
标题翻译：多层钨沉积工艺
公开(公告)号：US5489552A
公开(公告)日：1996-02-06
申请号：US366529
申请日：1994-12-30
申请人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
发明人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy
IPC分类号： C23C4/06 , C23C26/00 , H01L21/203 , H01L21/28 , H01L21/285 , H01L21/768 , H01L21/44 , H01L21/443
CPC分类号： H01L21/76838 , H01L21/28556
摘要： Tungsten plugs are formed in a manner which avoids the formation of unwanted tungsten volcanoes by depositing at least three and preferably five to seven layers of tungsten within a contact hole to form a layered plug. In particularly useful embodiments, the layers are deposited at alternating fast and slow rates of deposition.
摘要翻译：通过在接触孔内沉积至少三个，优选五至七层的钨以形成分层塞，避免形成不需要的钨火山的钨塞。在特别有用的实施方案中，以交替的快速和慢速沉积速率沉积这些层。

7. 发明授权

US6153452A Method of manufacturing semiconductor devices having improved polycide integrity through introduction of a silicon layer within the polycide structure 失效
标题翻译：通过在多晶硅化合物结构内引入硅层，制造具有改善的聚合物完整性的半导体器件的方法
公开(公告)号：US6153452A
公开(公告)日：2000-11-28
申请号：US782010
申请日：1997-01-07
申请人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy , Hem M. Vaidya
发明人： Sailesh M. Merchant , Arun K. Nanda , Pradip K. Roy , Hem M. Vaidya
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49
CPC分类号： H01L21/28061 , H01L21/823835 , H01L29/4933
摘要： Methods of manufacturing a semiconductor device. One method includes the steps of: (1) providing a substrate over which is to be deposited a metal silicide layer having a stoichiometric ratio within a desired range, (2) providing a target composed of a metal silicide, the target subject to degradation by reason of use, (3) sputtering atoms from the target to form the metal silicide layer over the substrate, the stoichiometric ratio subject to being without the desired range by reason of the degradation of the target and (4) depositing a predetermined amount of silicon on the metal silicide layer to return the stoichiometric ratio to within the desired range, a useful life of the target thereby increased.
摘要翻译：制造半导体器件的方法。一种方法包括以下步骤：（1）提供要在其上沉积化学计量比在所需范围内的金属硅化物层的衬底，（2）提供由金属硅化物组成的靶，靶由使用原因，（3）从靶上溅射原子以在衬底上形成金属硅化物层，化学计量比由于靶的劣化而不具有所需的范围，（4）沉积预定量的硅在金属硅化物层上以将化学计量比返回到所需范围内，从而靶的使用寿命增加。

8. 发明授权

US6071808A Method of passivating copper interconnects in a semiconductor 有权
标题翻译：钝化半导体中的铜互连的方法
公开(公告)号：US6071808A
公开(公告)日：2000-06-06
申请号：US339085
申请日：1999-06-23
申请人： Sailesh M. Merchant , Sudhanshu Misra , Pradip K. Roy
发明人： Sailesh M. Merchant , Sudhanshu Misra , Pradip K. Roy
IPC分类号： C23C16/40 , H01L21/28 , H01L21/304 , H01L21/306 , H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76867 , H01L21/321 , H01L21/3212 , H01L21/76849 , H01L21/32134
摘要： A method of passivating copper interconnects is disclosed. A freshly electrodeposited copper interconnect such as formed as via/trench structures in semiconductor manufacturing is chemically converted to passivating surface of copper tungstate or copper chromate either through MOCVD reaction with vapors of tungsten or chromium alkoxides, or by pyrolytic reaction with tungsten or chromium carbonyl in the presence of O.sub.2. The copper interconnect having the formed passivation service is then chemically mechanically polished. The process can be used with various manufacturing processes, including single and dual damascene processes.
摘要翻译：公开了一种钝化铜互连的方法。通过半导体制造中的通孔/沟槽结构形成的新电沉积铜互连物质通过与钨或铬醇盐的蒸气的MOCVD反应或通过与钨或铬羰基的热解反应而化学转化为钨酸铜或铬酸铜的钝化表面 O2的存在。然后对具有形成的钝化服务的铜互连进行化学机械抛光。该方法可用于各种制造工艺，包括单镶嵌和双镶嵌工艺。

9. 发明授权

US06403415B1 Semiconductor device having a metal barrier layer for a dielectric material having a high dielectric constant and a method of manufacture thereof 有权
标题翻译：具有介电常数介电材料用金属阻挡层的半导体装置及其制造方法
公开(公告)号：US06403415B1
公开(公告)日：2002-06-11
申请号：US09481463
申请日：2000-01-11
申请人： Glenn B. Alers , Sailesh M. Merchant , Pradip K. Roy
发明人： Glenn B. Alers , Sailesh M. Merchant , Pradip K. Roy
IPC分类号： H01L218242
CPC分类号： H01L28/56 , H01L21/31604 , H01L28/40 , H01L29/4966
摘要： The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device provides a capacitance to the integrated circuit and in a preferred embodiment comprises a first layer located on a surface of the integrated circuit. A metal barrier layer is located on the first layer and is susceptible to oxidation by oxygen. A high K capacitor dielectric layer (i.e., a higher K than silicon dioxide) that contains oxygen, such as tantalum pentoxide, is located over the metal barrier layer. The semiconductor device further includes a first layer located over the high K capacitor dielectric layer.
摘要翻译：本发明提供一种半导体器件，其具有用于电介质材料的金属阻挡层，如果需要，其可用于集成电路中。半导体器件为集成电路提供电容，并且在优选实施例中包括位于集成电路的表面上的第一层。金属阻挡层位于第一层上，易氧化氧。含有氧的高K电容电介质层（即比二氧化硅高的K），例如五氧化二钽，位于金属阻挡层的上方。半导体器件还包括位于高K电容介电层上的第一层。

10. 发明授权

US06359339B1 Multi-layered metal silicide resistor for Si Ic's 有权
标题翻译： Si Ic的多层金属硅化物电阻
公开(公告)号：US06359339B1
公开(公告)日：2002-03-19
申请号：US09480224
申请日：2000-01-10
申请人： Richard W. Gregor , Isik C. Kizilyalli , Sailesh M. Merchant , Jaseph R. Radosevich , Pradip K. Roy
发明人： Richard W. Gregor , Isik C. Kizilyalli , Sailesh M. Merchant , Jaseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L2348
CPC分类号： H01L28/24 , H01L27/0802
摘要： The present invention provides a unique a resistor formed on a semiconductor substrate. The resistor preferably comprises a first resistor layer that includes a first metal silicide, such as tungsten silicide, and nitrogen and that is formed on the substrate. The first layer has a first thickness and a concentration of nitrogen incorporated therein. The nitrogen concentration may be varied to obtain a desired resistive value of the resistor. Thus, depending on the concentration of nitrogen, a wide range of resistive values may be achieved. The resistor further comprises a second resistor layer with a second thickness that includes a second metal silicide and that is formed on the first resistor layer. Thus, the present invention provides a metal silicide-based resistor having nitrogen incorporated therein which allows the resistance of the resistor to be tailored to specific electrical applications. Yet at the same time, the resistor is far less susceptible to temperature and voltage variation than conventional diffused resistors and, thereby, provides a more precise resistor.
摘要翻译：本发明提供了形成在半导体衬底上的独特的电阻器。电阻器优选地包括第一电阻层，该第一电阻层包括第一金属硅化物，例如硅化钨和氮，并且形成在衬底上。第一层具有掺入其中的第一厚度和氮浓度。可以改变氮浓度以获得电阻器的期望电阻值。因此，取决于氮的浓度，可以实现宽范围的电阻值。电阻器还包括具有第二厚度的第二电阻层，该第二电阻层包括第二金属硅化物，并形成在第一电阻层上。因此，本发明提供一种其中结合有氮化物的金属硅化物基电阻器，其允许将电阻器的电阻定制为特定的电气应用。然而与此同时，电阻器比常规扩散电阻器更不易受温度和电压变化的影响，从而提供更精确的电阻器。

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