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1. 发明授权

US06313021B1 PMOS device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance 有权
标题翻译： PMOS器件具有用于改善硅化物完整性和增强的硼渗透电阻的层状硅栅极
公开(公告)号：US06313021B1
公开(公告)日：2001-11-06
申请号：US09416491
申请日：1999-10-12
申请人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
发明人： Sailesh M. Merchant , Joseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L213205
CPC分类号： H01L21/28035 , H01L21/28044 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4933 , H01L29/4941
摘要： The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.
摘要翻译：本发明提供了一种在半导体衬底上形成亚微米p型金属氧化物半导体（PMOS）结构的方法。该工艺包括在半导体衬底上形成栅极氧化物，通过以第一沉积速率沉积栅极氧化物上的第一栅极层，以栅极氧化物形成栅极层，并以第二沉积速率在第一层上沉积第二栅极层以在门结构内提供改进的应力调节。该工艺还包括在栅极上形成硅化物掺杂剂阻挡层。由于在栅极中存在改善的应力调节，硅化物掺杂剂势垒的完整性显着增强。这种增加的硅化物完整性防止在随后的制造工艺期间对硅化物掺杂剂阻挡层的显着损坏。因此，在形成与栅极结构相邻的源极和漏极区域期间，掺杂物势垒能够提供对掺杂剂穿透（例如硼）的预期程度的阻抗。

2. 发明授权

US5298436A Forming a device dielectric on a deposited semiconductor having sub-layers 失效
标题翻译：在具有子层的沉积半导体上形成器件电介质
公开(公告)号：US5298436A
公开(公告)日：1994-03-29
申请号：US76949
申请日：1993-06-16
申请人： Joseph R. Radosevich , Pradip K. Roy
发明人： Joseph R. Radosevich , Pradip K. Roy
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/3205 , H01L29/788 , H01L29/792 , H01L21/20
CPC分类号： H01L21/32055 , H01L21/28158 , H01L21/28273
摘要： A high quality dielectric layer, typically silicon dioxide, is formed on a multi-layer deposited semiconductor structure, typically polysilicon or amorphous silicon. The multi-layer structure is formed by varying the silicon deposition rate so as to obtain a low stress deposited silicon structure. The low stress allows for a higher quality dielectric to be formed on the exposed top surface. One application is for thin film transistor gate oxides. Other applications included capacitor dielectrics and the tunnel oxide on the floating gate of EEPROMs.
摘要翻译：通常在多层沉积的半导体结构（通常为多晶硅或非晶硅）上形成高质量的介电层，通常为二氧化硅。通过改变硅沉积速率形成多层结构，以获得低应力淀积硅结构。低应力允许在暴露的顶表面上形成更高质量的电介质。一种应用是薄膜晶体管栅极氧化物。其他应用包括电容器电介质和隧道氧化物在EEPROM的浮动栅极上。

3. 发明授权

US06537867B1 High speed low voltage semiconductor devices and method of fabrication 有权
标题翻译：高速低压半导体器件及其制造方法
公开(公告)号：US06537867B1
公开(公告)日：2003-03-25
申请号：US09630463
申请日：2000-08-02
申请人： Ronald L. Freyman , Isik C. Kizilyalli , Ross A. Kohler , Omkaram Nalamasu , Mark R. Pinto , Joseph R. Radosevich , Robert M. Vella , George P. Watson
发明人： Ronald L. Freyman , Isik C. Kizilyalli , Ross A. Kohler , Omkaram Nalamasu , Mark R. Pinto , Joseph R. Radosevich , Robert M. Vella , George P. Watson
IPC分类号： H01L21336
CPC分类号： H01L21/32139
摘要： A digit signal processor capable of operating at 100 MHZ with a 1.0 volt power supply. The digital signal processor is fabricated by application of strong phase-shift lithography to obtain a 0.12 &mgr;m gate dimension. A dual-mask process is utilized to improve resolution thereby producing high speed, low-voltage processors. A n+/p+ dual-Poly:Si module, and dopant penetration suppression techniques may be utilized.
摘要翻译：一个数字信号处理器能够以1.0伏的电源工作在100MHZ。数字信号处理器是通过应用强相移光刻技术制造的，以获得0.12μm的门尺寸。利用双掩模工艺来提高分辨率，从而产生高速，低电压处理器。可以使用n + / p +双Poly：Si模块和掺杂剂渗透抑制技术。

4. 发明授权

US06335557B1 Metal silicide as a barrier for MOM capacitors in CMOS technologies 有权
标题翻译：金属硅化物作为CMOS技术中MOM电容器的屏障
公开(公告)号：US06335557B1
公开(公告)日：2002-01-01
申请号：US09441561
申请日：1999-11-17
申请人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
IPC分类号： H01L2900
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/76838 , H01L27/0805
摘要： The present invention provides a semiconductor device having a metal oxide metal (MOM) capacitor formed over a semiconductor wafer. In one embodiment, the device is a MOM capacitor that includes a first metal layer formed over the semiconductor wafer, a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, located on the first metal layer and an oxide layer located on the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). Additionally, the metal silicide can act as an etch stop for the etching process. The MOM capacitor is completed by a second metal layer that is located on the oxide layer.
摘要翻译：本发明提供一种半导体器件，其具有在半导体晶片上形成的金属氧化物金属（MOM）电容器。在一个实施例中，器件是MOM电容器，其包括形成在半导体晶片上的第一金属层，位于第一金属层上的金属硅化物层，例如硅化钨，硅化物氮化物或难熔金属硅化物，以及氧化物层位于金属硅化物层上。在有利的实施例中，金属硅化物层可以是硅化钨氮化物，抵抗可能对晶片的其它部分进行的钝化的腐蚀作用，并且与氮化钛（TiN）不同，基本上不受脱镀工艺的影响。此外，金属硅化物可以用作蚀刻工艺的蚀刻停止。 MOM电容器由位于氧化物层上的第二金属层完成。

5. 发明授权

US06331460B1 Method of fabricating a mom capacitor having a metal silicide barrier 有权
标题翻译：制造具有金属硅化物屏障的母电容器的方法
公开(公告)号：US06331460B1
公开(公告)日：2001-12-18
申请号：US09441676
申请日：1999-11-17
申请人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
IPC分类号： H01L218242
CPC分类号： H01L23/5223 , H01L21/76843 , H01L21/76846 , H01L27/0805 , H01L28/75 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method of forming a metal oxide metal (MOM) capacitor over a semiconductor wafer. The method may include forming a first metal layer over the semiconductor wafer, forming a metal silicide layer, such as a tungsten silicide, silicide nitride or a refractory metal silicide, over the first metal layer and forming an oxide layer over the metal silicide layer. The metal silicide layer, which in an advantageous embodiment may be tungsten silicide nitride, resists the corrosive effects of deglazing that may be conducted on other portions of the wafer and is substantially unaffected by the deglazing process, unlike titanium nitride (TiN). The semiconductor device is completed by forming a second metal layer over the oxide layer.
摘要翻译：本发明提供一种在半导体晶片上形成金属氧化物金属（MOM）电容器的方法。该方法可以包括在半导体晶片之上形成第一金属层，在第一金属层上形成金属硅化物层，例如硅化钨，硅化物或难熔金属硅化物，并在金属硅化物层上形成氧化物层。在有利的实施例中，金属硅化物层可以是硅化钨氮化物，抵抗可能对晶片的其它部分进行的钝化的腐蚀作用，并且与氮化钛（TiN）不同，基本上不受脱镀工艺的影响。通过在氧化物层上形成第二金属层来完成半导体器件。

6. 发明授权

US06365511B1 Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability 有权
标题翻译：硅化钨氮化物作为高温退火的屏障，以提高热载体的可靠性
公开(公告)号：US06365511B1
公开(公告)日：2002-04-02
申请号：US09324946
申请日：1999-06-03
申请人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Sailesh M. Merchant , Joseph R. Radosevich
IPC分类号： H01L214763
CPC分类号： H01L21/76838 , H01L21/76841
摘要： The present invention provides a method of forming a metal stack structure over a substrate of a semiconductor device, comprising: (a) forming a first metal layer over the substrate, (b) forming a tungsten silicide nitride layer over the first metal layer, (c) forming a second metal layer over the tungsten silicide nitride layer, and (d) annealing the metal stack structure at a diffusion temperature. The tungsten silicide nitride layer inhibits diffusion of the metal in the metal stack. In one embodiment, the annealing is performed in the presence of a forming gas mixture comprising deuterium. In one particularly advantageous embodiment, the metal stack is formed in a contact opening or via. In yet other embodiments, the first metal layer may be a stack layer of titanium and titanium nitride and the second metal layer may be aluminum or copper.
摘要翻译：本发明提供一种在半导体器件的衬底上形成金属堆叠结构的方法，包括：（a）在衬底上形成第一金属层，（b）在第一金属层上形成硅化钨化物层，（ c）在所述硅化钨氮化物层上形成第二金属层，和（d）在扩散温度下退火所述金属堆叠结构。硅化钨层抑制金属堆叠中的金属的扩散。在一个实施方案中，在包含氘的形成气体混合物的存在下进行退火。在一个特别有利的实施例中，金属叠层形成在接触开口或通孔中。在其它实施例中，第一金属层可以是钛和氮化钛的堆叠层，第二金属层可以是铝或铜。

7. 发明授权

US5576240A Method for making a metal to metal capacitor 失效
标题翻译：制造金属对金属电容器的方法
公开(公告)号：US5576240A
公开(公告)日：1996-11-19
申请号：US353015
申请日：1994-12-09
申请人： Joseph R. Radosevich , Ranbir Singh
发明人： Joseph R. Radosevich , Ranbir Singh
IPC分类号： H01G4/10 , H01L21/02 , H01L21/822 , H01L27/04 , H01L21/70 , H01L27/00
CPC分类号： H01L28/40 , Y10S148/014
摘要： A method for making a metal-to-metal capacitor for an integrated circuit includes forming a layer of titanium/titanium nitride on a polysilicon which has been patterned with interlevel dielectrics. A capacitor dielectric is then deposited, followed by patterning with photoresist to delineate the capacitor, etching to remove extraneous dielectric, deposition of aluminum, further patterning and etching to define the capacitor and access area, and removal of photoresist.
摘要翻译：制造用于集成电路的金属 - 金属电容器的方法包括在已经用层间电介质图案化的多晶硅上形成钛/氮化钛层。然后沉积电容器电介质，然后用光致抗蚀剂图案化以描绘电容器，蚀刻去除外来电介质，沉积铝，进一步构图和蚀刻以限定电容器和存取区域以及去除光致抗蚀剂。

8. 发明授权

US06602758B2 Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing 有权
公开(公告)号：US06602758B2
公开(公告)日：2003-08-05
申请号：US09882961
申请日：2001-06-15
申请人： Isik C. Kizilyalli , Joseph R. Radosevich
发明人： Isik C. Kizilyalli , Joseph R. Radosevich
IPC分类号： H01L2176
CPC分类号： H01L21/02686 , H01L21/02381 , H01L21/02433 , H01L21/02488 , H01L21/02494 , H01L21/02532 , H01L21/02598 , H01L21/02609 , H01L21/2026 , H01L21/76248 , H01L21/84 , H01L27/1203
摘要： A method for forming single crystalline silicon-on-insulator (SOI) structures over a silicon substrate includes forming an amorphous silicon layer over an insulating layer and contacting the substrate through the insulating layer. An excimer laser having operating conditions and a wavelength chosen to selectively melt amorphous silicon irradiates the entire substrate surface and is largely non-absorbed by materials other than silicon when incident upon them. Heating of the substrate and other materials is therefore minimal. After a blanket radiation process selectively melts the amorphous silicon layer, cooling conditions are chosen such that a single crystal silicon film is formed during the solidification process due to contact to the single crystal silicon substrate which acts as a seed layer. Various devices may be formed on the SOI islands as well as on exposed portions of the substrate not covered by the SOI islands.

9. 发明授权

US06040616A Device and method of forming a metal to metal capacitor within an integrated circuit 失效
标题翻译：在集成电路内形成金属对金属电容器的装置和方法
公开(公告)号：US06040616A
公开(公告)日：2000-03-21
申请号：US909563
申请日：1997-08-12
申请人： Donald C. Dennis , Joseph R. Radosevich , Ranbir Singh
发明人： Donald C. Dennis , Joseph R. Radosevich , Ranbir Singh
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L29/00
CPC分类号： H01L28/40
摘要： The present invention provides, for use in an integrated circuit structure having a prior level that includes a foundation dielectric formed over a conductive polycrystalline material, a capacitor comprising first and second electrodes having a capacitor dielectric formed therebetween. The first electrode is formed immediately over the prior level and extends beyond a common area of the first and second electrodes and connects the capacitor to the prior level outside of the common area. The capacitor is free of a direct electrical contact with the prior level; that is, the capacitor is not connected to the prior level by a window or other interconnect structure that extends directly from the capacitor itself within the common area. Electrical connection of the capacitor to the prior level is made outside the common area of the capacitor.
摘要翻译：本发明提供了一种用于具有包括在导电多晶材料上形成的基底电介质的先前水平的集成电路结构的电容器，包括在其间形成有电容器电介质的第一和第二电极的电容器。第一电极立即形成在先前水平之上并且延伸超过第一和第二电极的公共区域，并将电容器连接到公共区域外的先前水平。电容器与前一级无直接电接触; 也就是说，电容器没有通过直接从公共区域内的电容器本身延伸的窗口或其它互连结构连接到先前的电平。在电容器的公共区域之外，将电容器的电连接到先前的电平。

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