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1. 发明授权

US5396465A Circuit for controlling isolation transistors in a semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的隔离晶体管的电路
公开(公告)号：US5396465A
公开(公告)日：1995-03-07
申请号：US156779
申请日：1993-11-24
申请人： Seung-Cheol Oh , Yong-Sik Seok
发明人： Seung-Cheol Oh , Yong-Sik Seok
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C7/1006 , G11C29/50 , G11C11/401
摘要： A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.
摘要翻译：半导体存储器件具有设置在公共位读出放大器和存储器阵列之间的相邻存储器阵列和隔离晶体管。根据本发明的隔离控制电路在老化操作模式期间产生电源电压Vcc（而不是升压电压Vpp），从而防止隔离晶体管的栅极氧化层被破坏或劣化。

2. 发明授权

US08736532B2 Liquid crystal display device having a 1-dot inversion or 2-dot inversion scheme and method thereof 有权
标题翻译：具有1点反转或2点反转方案的液晶显示装置及其方法
公开(公告)号：US08736532B2
公开(公告)日：2014-05-27
申请号：US13333140
申请日：2011-12-21
申请人： Seung-Cheol Oh
发明人： Seung-Cheol Oh
IPC分类号： G09G3/36
CPC分类号： G09G3/2092 , G09G3/3648
摘要： A liquid crystal display device includes a liquid crystal panel including a plurality of gate lines (GL1 to GLn) data lines (DL1 to DLm) and a plurality of pixel areas; a timing controller arranging the external input image data to be proper to the driving of the liquid crystal panel, generating a gate control signal (GCS) and a data control signal (DCS), and grouping the arranged image data into a plurality of groups each having a plurality of controller channels, and outputting a group control signal (HINV_m) by determining whether the arranged image data for each group is proper to horzintal-1-dot inversion or horizontal-2-dot inversion; a gate driver driving the plurality of the gate lines of the liquid crystal panel based on the gate control signal (GCS) from the timing controller; and a data driver grouping output terminals into a plurality of groups.
摘要翻译：液晶显示装置包括：液晶面板，包括多条栅极线（GL1〜GLn），数据线（DL1〜DLm）和多个像素区域; 定时控制器，将外部输入图像数据配置为适合于液晶面板的驱动，产生门控制信号（GCS）和数据控制信号（DCS），并将排列的图像数据分组成多个组具有多个控制器通道，并且通过确定每组的排列图像数据是否适合于水平1点反转或水平2点反转来输出组控制信号（HINV_m）; 基于来自定时控制器的栅极控制信号（GCS）驱动液晶面板的多条栅极线的栅极驱动器; 以及将输出终端分组成多个组的数据驱动器。

3. 发明授权

US5461587A Row redundancy circuit and method for a semiconductor memory device with a double row decoder 失效
标题翻译：具有双列解码器的半导体存储器件的行冗余电路和方法
公开(公告)号：US5461587A
公开(公告)日：1995-10-24
申请号：US343950
申请日：1994-11-17
申请人： Seung-Cheol Oh
发明人： Seung-Cheol Oh
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C29/24 , G11C7/00
CPC分类号： G11C29/808 , G11C29/24
摘要： A row redundancy circuit for use in a semiconductor memory device having one memory cell array, and first and second main row decoders and first and second spare row decoders formed on both sides of the memory cell array includes a first fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the first spare row decoder, a second fuse box for receiving addresses and, during the occurrence of a defective address out of the received addresses, cutting a fuse on an input path of the defective address, thereby to supply an output signal to the second spare row decoder, and a row redundancy control circuit for receiving the output signals of the first and second fuse boxes and selectively supplying an output signal responsive to the received input signal level to the first and second spare row decoders.
摘要翻译：一种在具有一个存储单元阵列的半导体存储器件中使用的行冗余电路，以及形成在存储单元阵列两侧的第一和第二主行解码器以及第一和第二备用行解码器，包括用于接收地址的第一保险丝盒，在接收到的地址中发生缺陷地址时，切断缺陷地址的输入路径上的保险丝，从而向第一备用行解码器提供输出信号，第二保险丝盒用于接收地址，并且在发生期间从接收到的地址中的缺陷地址中切出缺陷地址的输入路径上的熔丝，从而向第二备用行解码器提供输出信号，以及行冗余控制电路，用于接收第一和第第二保险丝盒，并且响应于所接收的输入信号电平选择性地将输出信号提供给第一和第二备用行解码器。

4. 发明授权

US5355339A Row redundancy circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的行冗余电路
公开(公告)号：US5355339A
公开(公告)日：1994-10-11
申请号：US91839
申请日：1993-07-13
申请人： Seung-Cheol Oh , Moon-Gone Kim
发明人： Seung-Cheol Oh , Moon-Gone Kim
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/808 , G11C29/78
摘要： Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.
摘要翻译：公开了一种具有冗余的半导体器件，用于用附加备用单元替换具有预定缺陷的存储单元。在具有多个正常子存储阵列的半导体存储器件中，本发明公开了一种冗余技术，其允许任何冗余地址解码器与任何子存储阵列一起使用。这可以最大限度地提高冗余维修的效率，并最大限度地提高芯片面积的使用。

5. 发明授权

US6064622A Column select line control circuit for synchronous semiconductor memory device and associated methods 有权
标题翻译：用于同步半导体存储器件的列选择线控制电路及相关方法
公开(公告)号：US6064622A
公开(公告)日：2000-05-16
申请号：US221827
申请日：1998-12-28
申请人： Hi-Choon Lee , Seung-Cheol Oh
发明人： Hi-Choon Lee , Seung-Cheol Oh
IPC分类号： G11C11/413 , G11C7/10 , G11C11/407 , G11C8/00
CPC分类号： G11C7/1048
摘要： A synchronous memory includes a column main-decoder circuit that is directly coupled to column select lines (CSL), and a timing controller that controls both enable timing and disable timing of the column select lines by controlling the column pre-decoder. The CSL timing controller generates a CSL timing control signal representative of the enable timing and the disable timing of the column select lines. The column pre-decoder is either enabled or disabled depending upon logic states of the CSL timing control signal. The timing controller includes a first control circuit which provides a CSL enable control signal, a CSL disable control circuit which provides a CSL disable control signal, and a flip-flop circuit which receives the CSL enable and disable control signals and provides the CSL timing control signal.
摘要翻译：同步存储器包括直接耦合到列选择线（CSL）的列主解码器电路，以及定时控制器，其通过控制列预解码器来控制列选择线的启用定时和禁止定时。 CSL定时控制器产生表示列选择线的使能定时和禁止定时的CSL定时控制信号。根据CSL定时控制信号的逻辑状态，列预解码器被启用或禁用。定时控制器包括提供CSL使能控制信号的第一控制电路，提供CSL禁止控制信号的CSL禁止控制电路和接收CSL使能和禁止控制信号并提供CSL定时控制的触发器电路信号。

6. 发明授权

US5793074A Metal oxide semiconductor capacitors having uniform C-V characteristics over an operating range and reduced susceptibility to insulator breakdown 失效
标题翻译：金属氧化物半导体电容器在工作范围内具有均匀的C-V特性，并降低对绝缘体击穿的敏感性
公开(公告)号：US5793074A
公开(公告)日：1998-08-11
申请号：US684464
申请日：1996-07-19
申请人： Hoon Choi , Seung-Cheol Oh
发明人： Hoon Choi , Seung-Cheol Oh
IPC分类号： H01L27/04 , H01L21/822 , H01L29/94 , H01L27/108
CPC分类号： H01L29/94
摘要： A MOS capacitor has uniform C-V capacitance characteristics across an operating voltage range and has reduced susceptibility to insulator breakdown and includes a semiconductor substrate of first conductivity type, a region of insulating material on an upper surface of the substrate and a well region of second conductivity type extending adjacent the region of insulating material. The well region is spaced from the region of insulating material so that the substrate extends to the upper surface therebetween. A source region of second conductivity type is formed in the well region. An insulating layer is formed on the source region and extends over the region of insulating material. A first electrode is formed on the insulating layer and a second electrode is formed on the source region. The capacitor also includes a P-N junction established between the source region of second conductivity type and the region of insulating material beneath the insulating layer. This P-N junction provides the capacitor with substantially uniform capacitance characteristics when a voltage is applied between the first electrode and the second electrode. Furthermore, because some of the voltage differential is established across the P-N junction during operation, the electric field at the corner of the region of insulating material and the insulating layer is reduced.
摘要翻译： MOS电容器在工作电压范围内具有均匀的CV电容特性，并且降低了对绝缘体击穿的敏感性，并且包括第一导电类型的半导体衬底，衬底上表面上的绝缘材料区域和第二导电类型的阱区在绝缘材料的区域附近延伸。阱区域与绝缘材料的区域隔开，使得衬底延伸到它们之间的上表面。在阱区中形成第二导电类型的源区。绝缘层形成在源极区域上并在绝缘材料的区域上延伸。第一电极形成在绝缘层上，第二电极形成在源极区上。电容器还包括在第二导电类型的源极区域和绝缘层下方的绝缘材料区域之间建立的P-N结。当在第一电极和第二电极之间施加电压时，该P-N结为电容器提供基本均匀的电容特性。此外，由于在工作期间跨越P-N结建立了一些电压差，所以绝缘材料区域和绝缘层的拐角处的电场减小。

7. 发明授权

US5754075A Integrated circuits including power supply boosters and methods of operating same 失效
标题翻译：集成电路，包括电源增压器和操作方法
公开(公告)号：US5754075A
公开(公告)日：1998-05-19
申请号：US649427
申请日：1996-05-16
申请人： Seung-Cheol Oh , Hoon Choi
发明人： Seung-Cheol Oh , Hoon Choi
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , G05F1/10
CPC分类号： G11C5/145 , G11C8/08
摘要： An integrated circuit provides a power supply voltage, a first boosted voltage, and a second boosted voltage which is preferably equal to or greater than the first boosted voltage, to the integrated circuit transistors, such that the integrated circuit transistors operate using the power supply voltage, the first boosted voltage and the second boosted voltage. The integrated circuit includes a first boosting circuit which boosts the power supply voltage to a first boosted voltage and a second boosting circuit which boosts the power supply voltage to a second boosted voltage. The first boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and the second boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and to an enable signal. Preferably, the first boosting circuit applies the first boosted voltage to the bulk region of selected PMOS transistors in the integrated circuit and the second boosting circuit applies the second boosting voltage to the source regions of selected PMOS transistors. In one embodiment, the first and second boosted voltages are applied to the word line driver of an integrated circuit memory device such that the second boosted voltage is applied to the source of the word line driver PMOS transistors in response to a row address strobe signal. High speed operations are thereby provided with reduced susceptibility to bridging defect errors.
摘要翻译：集成电路向集成电路晶体管提供优选等于或大于第一升压电压的电源电压，第一升压电压和第二升压电压，使得集成电路晶体管使用电源电压，第一升压电压和第二升压电压。集成电路包括将电源电压升高到第一升压电压的第一升压电路和将电源电压升高到第二升压电压的第二升压电路。第一升压电路优选地响应于向集成电路施加电源电压，并且第二升压电路优选地响应于将电源电压施加到集成电路和使能信号。优选地，第一升压电路将第一升压电压施加到集成电路中所选择的PMOS晶体管的体区，并且第二升压电路将第二升压电压施加到所选PMOS晶体管的源极区。在一个实施例中，第一和第二升压电压被施加到集成电路存储器件的字线驱动器，使得响应于行地址选通信号将第二升压电压施加到字线驱动器PMOS晶体管的源极。因此，提供了高速度操作，降低了对桥接缺陷错误的敏感性。

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