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1. 发明授权

US08339870B2 High voltage generating circuit and semiconductor memory device having the same and method thereof 失效
标题翻译：高电压发生电路及其半导体存储器件及其方法
公开(公告)号：US08339870B2
公开(公告)日：2012-12-25
申请号：US13067404
申请日：2011-05-31
申请人： Sang-hyuk Kwon , Hi-choon Lee
发明人： Sang-hyuk Kwon , Hi-choon Lee
IPC分类号： G11C5/14
CPC分类号： G11C5/147 , G11C11/406 , G11C11/4074
摘要： A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters.
摘要翻译：高压发生电路可以包括脉冲信号发生器，计数器，多个发射器和/或多个泵器。脉冲信号发生器可以被配置为响应于刷新命令信号被使能以输出脉冲信号。计数器可以被配置为对脉冲信号进行计数并顺序地输出多个选择信号。多个发射机可以被配置为响应于多个选择信号的各个选择信号而被顺序启用以发送脉冲信号。多个泵器可以对应于多个发射器。多个泵器中的每一个可以被配置为基于来自多个发射器的相应发射器的所发射的脉冲信号共同地产生高电压。

2. 发明授权

US07961535B2 Test circuit and method for use in semiconductor memory device 有权
标题翻译：用于半导体存储器件的测试电路和方法
公开(公告)号：US07961535B2
公开(公告)日：2011-06-14
申请号：US12155512
申请日：2008-06-05
申请人： Hi-Choon Lee
发明人： Hi-Choon Lee
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/26 , G11C2029/1202
摘要： A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled.
摘要翻译：提供了一种用于半导体存储器件的测试电路和方法。在包括多个存储块的半导体存储器件中使用的测试方法可以包括通过对字线施加应力并且响应于顺序施加的测试地址来执行测试操作来顺序启用多个字线，每个字从多个存储器块顺序选择并使能。

3. 发明授权

US07574636B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07574636B2
公开(公告)日：2009-08-11
申请号：US11561023
申请日：2006-11-17
申请人： Hi-Choon Lee , Sung-Bum Cho
发明人： Hi-Choon Lee , Sung-Bum Cho
IPC分类号： G11C29/00
CPC分类号： G11C29/14 , G11C29/1201 , G11C2029/2602
摘要： The present invention provides a semiconductor memory device comprising a memory cell array including a plurality of memory regions, an address decoding portion for decoding an address applied from an external portion for simultaneously selecting all of the plurality of memory regions during a test read operation, a data IO control portion for receiving test pattern data and writing the test pattern data to each of the plurality of memory regions during a test write operation, and reading the test pattern data from one of the plurality of memory regions and outputting the test pattern data during the test read operation, a data IO portion for receiving the test pattern data from the external portion and applying the test pattern data to the data IO control portion during the test write operation, and receiving the test pattern data output from the data IO control portion and conditionally outputting the test pattern data as test status data to the external portion in response to an output control signal during the test read operation, and a test control signal generating portion for comparing the test pattern data read from the plurality of memory regions to generate the output control signal for conditionally outputting the test pattern data as the test status data during the test read operation.
摘要翻译：本发明提供一种包括存储单元阵列的半导体存储器件，该存储单元阵列包括多个存储区域，地址解码部分，用于解码从外部部分施加的地址，用于在测试读取操作期间同时选择所有多个存储器区域; 数据IO控制部分，用于在测试写入操作期间接收测试图案数据并将测试图案数据写入到多个存储器区域中的每一个，并且从多个存储区域中的一个读取测试图案数据，并在测试读取操作，用于从外部部分接收测试图案数据并在测试写入操作期间将测试图案数据应用于数据IO控制部分的数据IO部分，以及从数据IO控制部分输出的测试图案数据并响应于外部条件将测试图形数据作为测试状态数据输出到外部部分在测试读取操作期间放置控制信号，以及测试控制信号生成部分，用于比较从多个存储区域读取的测试图形数据，以产生输出控制信号，用于有条件地输出测试模式数据作为测试状态数据读操作。

4. 发明申请

US20090116305A1 WORD LINE DRIVER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
标题翻译：具有相同功能的字线驱动器和半导体存储器件
公开(公告)号：US20090116305A1
公开(公告)日：2009-05-07
申请号：US12260206
申请日：2008-10-29
申请人： Chris Ji-Yoon SON , Hi-Choon LEE
发明人： Chris Ji-Yoon SON , Hi-Choon LEE
IPC分类号： G11C7/00 , G11C8/08 , G11C5/14
CPC分类号： G11C8/08 , G11C11/406 , G11C11/4087 , G11C2211/4065 , G11C2211/4067
摘要： A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode.
摘要翻译：用于半导体存储器件的字线驱动器包括升压电压发生器，子字线驱动器和主字线驱动器。升压电压发生器通过接收内部电源电压和泵送电荷而产生升压电压。子字线驱动器接收内部电源电压，并且在命令操作模式下将内部电源电压提供给升压节点之后激活升压电压控制信号。主字符驱动器通过在正常工作模式下响应于升压电压控制信号而将升压电压提供给升压节点来实现字线，并且在将字线升压到内部电源之后使得具有升压电压的字线在指令运行模式下，通过将升压节点从内部电源电压改变为升压电压来提供电压。

5. 发明授权

US07480196B2 Semiconductor device generating a test voltage for a wafer burn-in test and method thereof 有权
标题翻译：产生晶片老化测试的测试电压的半导体器件及其方法
公开(公告)号：US07480196B2
公开(公告)日：2009-01-20
申请号：US11651973
申请日：2007-01-11
申请人： Jin-Hyung Cho , Hi-Choon Lee
发明人： Jin-Hyung Cho , Hi-Choon Lee
IPC分类号： G11C7/00
CPC分类号： G11C29/12 , G01R31/3004 , G11C29/006 , G11C29/12005 , G11C2029/1204
摘要： A semiconductor device for generating a test voltage for a wafer burn-in test and method thereof is disclosed. To generate the test voltage for a wafer burn-in test, a control signal may be generated in response to a supply voltage from an external wafer burn-in test device. A supplementary voltage may be generated in response to the control signal by using an internal voltage driving circuit. The test voltage may be generated by combining the supply voltage and the supplementary voltage.
摘要翻译：公开了一种用于生成晶片老化测试的测试电压的半导体器件及其方法。为了产生用于晶片老化测试的测试电压，可以响应于来自外部晶片老化测试装置的电源电压而产生控制信号。可以通过使用内部电压驱动电路来响应于控制信号产生辅助电压。可以通过组合电源电压和辅助电压来产生测试电压。

6. 发明授权

US07460418B2 Semiconductor memory device for stack package and read data skew control method thereof 有权
标题翻译：半导体存储器件，用于堆栈封装和读取数据偏移控制方法
公开(公告)号：US07460418B2
公开(公告)日：2008-12-02
申请号：US11746734
申请日：2007-05-10
申请人： Won-chang Jung , Hi-choon Lee
发明人： Won-chang Jung , Hi-choon Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/105 , H01L2224/14181 , H01L2224/16145
摘要： A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.
摘要翻译：在半导体存储器件及其读出数据偏移控制方法中，可以使用堆叠封装中的焊盘接合来控制读出数据被输出的时间点。半导体存储器件包括接合选择焊盘和延迟控制电路，该延迟控制电路根据施加到焊接选择焊盘的信号的逻辑状态来控制数据从输出缓冲器输出的时间点。因此，当在堆叠封装中使用半导体存储器件时，可以通过将焊接选择焊盘连接到接地电压或电源电压来补偿由于接合线上的负载而产生的读取数据偏斜。

7. 发明授权

US07420861B2 Semiconductor memory device and data read and write method thereof 失效
标题翻译：半导体存储器件及其数据读写方法
公开(公告)号：US07420861B2
公开(公告)日：2008-09-02
申请号：US11558398
申请日：2006-11-09
申请人： Hi-Choon Lee , Wol-Jin Lee
发明人： Hi-Choon Lee , Wol-Jin Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C11/4097 , G11C2207/002 , G11C2207/229
摘要： A semiconductor memory device includes first and second global data line pairs connected to a local data line pair, allowing a reduced pre-charge voltage that lowers current consumption and increases operating speed. Also included are a sense amplifier for amplifying data of the second global data line pair and outputting the amplified data to a data line, and a write driver for outputting data of the data line to the first global data line pair during a write operation. Switching circuits are connected between the first and second global data line pairs, and the local data line and the first global data line pairs. The memory device further includes a first global data line pre-charge circuit for pre-charging the first global data line pair to a first voltage level, and a second global data line pre-charge circuit for pre-charging the second global data line pair to a second voltage level.
摘要翻译：半导体存储器件包括连接到本地数据线对的第一和第二全局数据线对，允许减少的预充电电压降低电流消耗并增加操作速度。还包括用于放大第二全局数据线对的数据并将放大的数据输出到数据线的读出放大器，以及用于在写入操作期间将数据线的数据输出到第一全局数据线对的写入驱动器。开关电路连接在第一和第二全局数据线对之间，以及本地数据线和第一全局数据线对之间。存储器件还包括用于将第一全局数据线对预充电到第一电压电平的第一全局数据线预充电电路和用于对第二全局数据线对进行预充电的第二全局数据线预充电电路达到第二电压电平。

8. 发明申请

US20080043548A1 SEMICONDUCTOR MEMORY DEVICE FOR STACK PACKAGE AND READ DATA SKEW CONTROL METHOD THEREOF 有权
标题翻译：用于堆叠封装的半导体存储器件及其数据读取控制方法
公开(公告)号：US20080043548A1
公开(公告)日：2008-02-21
申请号：US11746734
申请日：2007-05-10
申请人： Won-chang Jung , Hi-choon Lee
发明人： Won-chang Jung , Hi-choon Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G11C7/1057 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C2207/105 , H01L2224/14181 , H01L2224/16145
摘要： A semiconductor memory device and a read data skew control method thereof, in which a point of time when read data is output can he controlled using pad bonding in stack packages. The semiconductor memory device includes a bonding option pad and a delay control circuit that controls the point of time when data is output from an output buffer depending on logic states of a signal applied to the bonding option pad. Thus, when using the semiconductor memory device in stack packages, the read data skew generated as a result of a load on a bonding wire can be compensated by connecting the bonding option pad to ground voltage or a supply voltage.
摘要翻译：在半导体存储器件及其读出数据偏移控制方法中，可以使用堆叠封装中的焊盘接合来控制读出数据被输出的时间点。半导体存储器件包括接合选项焊盘和延迟控制电路，该延迟控制电路根据施加到焊接选项焊盘的信号的逻辑状态来控制数据从输出缓冲器输出的时间点。因此，当在堆叠封装中使用半导体存储器件时，可以通过将焊接选择焊盘连接到接地电压或电源电压来补偿由于接合线上的负载而产生的读取数据偏斜。

9. 发明申请

US20070283198A1 Parallel bit test circuits for testing semiconductor memory devices and related methods 有权
标题翻译：用于测试半导体存储器件的并行位测试电路及相关方法
公开(公告)号：US20070283198A1
公开(公告)日：2007-12-06
申请号：US11500126
申请日：2006-08-07
申请人： Hi-Choon Lee
发明人： Hi-Choon Lee
IPC分类号： G01R31/28
CPC分类号： G11C29/40 , G11C29/44 , G11C2029/2602
摘要： An integrated circuit device includes a test circuit and at least one flag generator circuit. The test circuit is configured to generate first and second sets of test results in parallel in response to a memory test operation. The first and second sets of test results respectively correspond to first and second memory banks. The test circuit is further configured to merge respective ones of the first set of test results with respective ones of the second set of test results to provide a set of merged test results to respective ones of a set of output terminals of the integrated circuit device. The at least one flag generator circuit is configured to generate a first flag signal that indicates a presence of at least one memory test error in the first set of test results, and a second flag signal that indicates a presence of at least one memory test error in the second set of test results. Based on the set of merged test results and the first and second flag signals, the test circuit may determine which of the memory blocks of the first and second memory banks includes a defective memory cell therein. Related methods are also discussed.
摘要翻译：集成电路装置包括测试电路和至少一个标志发生器电路。测试电路被配置为响应于存储器测试操作并行地产生第一和第二组测试结果。第一组和第二组测试结果分别对应于第一和第二存储体。测试电路还被配置为将第一组测试结果中的相应测试结果与第二组测试结果中的相应测试结果合并，以向集成电路设备的一组输出终端中的相应测试结果提供一组合并的测试结果。所述至少一个标志发生器电路被配置为产生指示在所述第一组测试结果中存在至少一个存储器测试错误的第一标志信号，以及指示存在至少一个存储器测试错误的第二标志信号在第二组测试结果中。基于合并的测试结果集合和第一和第二标志信号，测试电路可以确定第一和第二存储器组中的哪些存储块包括其中的有缺陷的存储单元。还讨论了相关方法。

10. 发明申请

US20070014167A1 Semiconductor memory device with reduced multi-row address testing 有权
标题翻译：半导体存储器件具有减少的多行地址测试功能
公开(公告)号：US20070014167A1
公开(公告)日：2007-01-18
申请号：US11486184
申请日：2006-07-13
申请人： Hi-choon Lee
发明人： Hi-choon Lee
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C29/34 , G11C29/785 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor memory device and multi-row address test method reduce the time it takes to perform the multi-row address test. The semiconductor memory device comprises normal memory cell blocks, which can include normal memory cells and spare cells that replace defective cells. The device also includes a redundancy signal generator to output a redundancy signal indicating whether any memory cell blocks include defective cells and address signals of repair word lines corresponding to the defective cells. A redundancy signal decoder decodes the redundancy signal and the address signals of the repair word lines and outputs word line enable signals, and word line drivers that do not enable the repair word lines, but selectively enable the normal word lines in response to the word line enable signals.
摘要翻译：半导体存储器件和多行地址测试方法减少了执行多行地址测试所需的时间。半导体存储器件包括正常存储器单元块，其可以包括正常存储器单元和替代有缺陷单元的备用单元。该装置还包括冗余信号发生器，用于输出指示任何存储单元块是否包含有缺陷单元的冗余信号和对应于有缺陷单元的维修字线的地址信号。冗余信号解码器对修复字线的冗余信号和地址信号进行解码并输出字线使能信号，以及不启用修复字线的字线驱动器，但是响应于字线选择性地启用正常字线启用信号。

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