专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5355339A Row redundancy circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的行冗余电路
公开(公告)号：US5355339A
公开(公告)日：1994-10-11
申请号：US91839
申请日：1993-07-13
申请人： Seung-Cheol Oh , Moon-Gone Kim
发明人： Seung-Cheol Oh , Moon-Gone Kim
IPC分类号： G11C11/401 , G11C29/00 , G11C29/04 , H01L27/10 , G11C7/00
CPC分类号： G11C29/808 , G11C29/78
摘要： Disclosed is a semiconductor device with redundancy for replacing a memory cell with a predetermined defect with additional spare cells. In a semiconductor memory device having a plurality of normal submemory arrays, the present invention discloses a redundancy technique that allows any redundant address decoder to be used with any of the submemory arrays. This maximizes efficiency in redundant repairs as well as maximizes the use of the chip area.
摘要翻译：公开了一种具有冗余的半导体器件，用于用附加备用单元替换具有预定缺陷的存储单元。在具有多个正常子存储阵列的半导体存储器件中，本发明公开了一种冗余技术，其允许任何冗余地址解码器与任何子存储阵列一起使用。这可以最大限度地提高冗余维修的效率，并最大限度地提高芯片面积的使用。

2. 发明授权

US5315557A Semiconductor memory device having self-refresh and back-bias circuitry 失效
标题翻译：具有自刷新和反向偏置电路的半导体存储器件
公开(公告)号：US5315557A
公开(公告)日：1994-05-24
申请号：US980951
申请日：1992-11-25
申请人： Moon-Gone Kim , Sei-Seung Yoon
发明人： Moon-Gone Kim , Sei-Seung Yoon
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/402 , G11C7/02
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies and a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors. A back-bias generator having an oscillator and a back-bias voltage detecting circuit and a selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal. The oscillator output, together with the output of the back-bias control pulse generator, cause a driver control circuit to feed a drive signal to a charge pump during a self-refresh operation.
摘要翻译：半导体存储器件包括用于产生刷新时钟脉冲的刷新定时器，用于产生预定数量的不同频率的信号的二进制计数器和用于响应于从二进制计数器发送的信号产生自刷新使能信号的电路。还包括背偏置时钟脉冲发生器，其具有第一，第二和第三选择器，其中第三选择器响应于从第一和第二选择器中的每个选择器输出的信号，选择从二进制计数器发送的信号之一。具有振荡器和背偏电压检测电路的背偏置发生器和用于从反偏压检测电路接收输出信号的选择电路。响应于自刷新使能信号，信号被发送到振荡器。振荡器输出与反向偏置控制脉冲发生器的输出一起导致驱动器控制电路在自刷新操作期间将驱动信号馈送到电荷泵。

3. 发明授权

US5682117A Half power supply voltage generating circuit in a semiconductor memory device 失效
标题翻译：半导体存储器件中的半电源电压产生电路
公开(公告)号：US5682117A
公开(公告)日：1997-10-28
申请号：US660213
申请日：1996-06-03
申请人： Hoon Choi , Moon-Gone Kim
发明人： Hoon Choi , Moon-Gone Kim
IPC分类号： G11C11/413 , G05F3/24 , G11C11/407 , G05F1/10
CPC分类号： G05F3/247
摘要： A half Vcc generating circuit generates an accurate half supply voltage with high driving power. The half Vcc generating circuit includes a bias circuit supplied with an internal supply voltage and a driving circuit supplied with an external supply voltage. The internal supply voltage is independent of and lower than the external supply voltage.
摘要翻译：一半Vcc发生电路产生具有高驱动功率的准确的半电源电压。半Vcc的生成电路包括具有内部电源电压和与外部电源电压供电的驱动电路提供的偏置电路。内部电源电压独立于和低于外部电源电压。

4. 发明授权

US5790464A Method for arranging a memory cell array in semiconductor memory device 失效
标题翻译：用于在半导体存储器件中布置存储单元阵列的方法
公开(公告)号：US5790464A
公开(公告)日：1998-08-04
申请号：US580213
申请日：1995-12-28
申请人： Jae-Gu Roh , Moon-Gone Kim
发明人： Jae-Gu Roh , Moon-Gone Kim
IPC分类号： G11C8/14 , G11C29/00 , G11C7/00
CPC分类号： G11C29/80 , G11C29/84 , G11C8/14
摘要： A method of arranging a memory cell array in a semiconductor memory device, comprising the steps of dividing the memory cell array into a plurality of memory cell array areas having equal size, providing within the memory cell array a plurality of sub-normal memory cell arrays and at least one redundant memory cell array, arranging the plurality of sub-normal memory cell arrays and the at least one redundant memory cell array into the plurality of memory cell array areas, and arranging a plurality of sub-normal word line drivers, such that each sub-normal word line driver is adjacent to one of the plurality of memory cell array areas.
摘要翻译：一种在半导体存储器件中布置存储单元阵列的方法，包括以下步骤：将存储单元阵列划分成具有相同尺寸的多个存储单元阵列区域，在存储单元阵列内提供多个子正常存储单元阵列以及至少一个冗余存储单元阵列，将所述多个子正常存储单元阵列和所述至少一个冗余存储单元阵列布置到所述多个存储单元阵列区域中，以及布置多个子正常字线驱动器，每个子正常字线驱动器与多个存储单元阵列区域中的一个相邻。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式