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1. 发明授权

US06721210B1 Voltage boosting circuit for a low power semiconductor memory 失效
标题翻译：低功耗半导体存储器的升压电路
公开(公告)号：US06721210B1
公开(公告)日：2004-04-13
申请号：US10232852
申请日：2002-08-30
申请人： Seung Cheol Oh , Paul S. Lazar
发明人： Seung Cheol Oh , Paul S. Lazar
IPC分类号： G11C700
CPC分类号： G11C11/4085 , G11C5/145 , G11C11/417 , G11C2207/2227
摘要： An improved voltage boosting circuit operates entirely from a single, common VCC voltage supply. An NMOS pass transistor has a gate input terminal to which is connected a gate boost capacitor and a PMOS precharge circuit. A drain terminal of the NMOS pass transistor is connected to a drain boost capacitor and to a drain precharge circuit. The gate boost capacitor is precharged from the common VCC voltage. The second terminal of the precharged gate boost capacitor is connected to the common VCC voltage level to thereby boost the precharged gate input terminal voltage to 2 VCC. The drain of the NMOS pass transistor has a similar boost capacitor and precharge configuration. Another embodiment further includes an additional gate preboost capacitor and a gate preboost precharge circuit for boosting the gate voltage to 3 VCC to more efficiently drive the NMOS pass transistor.
摘要翻译：改进的升压电路完全由单一的公共VCC电压供电。 NMOS传输晶体管具有栅极输入端子，栅极升压电容器和PMOS预充电电路连接到栅极输入端子。 NMOS传输晶体管的漏极端子连接到漏极升压电容器和漏极预充电电路。栅极升压电容器从公共VCC电压预充电。预充电栅极升压电容器的第二端子连接到公共VCC电压电平，从而将预充电栅极输入端子电压升压到2 VCC。 NMOS传输晶体管的漏极具有类似的升压电容器和预充电配置。另一个实施例还包括附加的栅极预引脚电容器和用于将栅极电压升压到3VV以更有效地驱动NMOS传输晶体管的栅极预充电电路。

2. 发明授权

US5959904A Dynamic column redundancy driving circuit for synchronous semiconductor memory device 失效
标题翻译：用于同步半导体存储器件的动态列冗余驱动电路
公开(公告)号：US5959904A
公开(公告)日：1999-09-28
申请号：US953351
申请日：1997-10-17
申请人： Seung-cheol Oh
发明人： Seung-cheol Oh
IPC分类号： G11C11/407 , G11C7/00 , G11C11/401 , G11C29/00 , G11C29/04
CPC分类号： G11C7/1072 , G11C29/785 , G11C2029/4402
摘要： A dynamic column redundancy driving circuit for a synchronous semiconductor memory device is provided. The circuit includes a first node, a precharging portion, an address determining portion, a clock delay portion, and a driving portion. The precharging portion precharges the first node in the first phase of the clock. The address determining portion is connected to the first node and includes a plurality of fuses selectively disconnected according to a defect address and changes a logic level of the first node in the second phase of the clock according to whether an address matches the defect address. The clock delay portion delays the clock. The driving portion receives the output of the address determining portion and the output of the clock delay portion and produces a redundancy wordline driving signal.
摘要翻译：提供了一种用于同步半导体存储器件的动态列冗余驱动电路。电路包括第一节点，预充电部分，地址确定部分，时钟延迟部分和驱动部分。预充电部分在时钟的第一阶段预充电第一节点。地址确定部分连接到第一节点并且包括根据缺陷地址选择性地断开的多个熔丝，并且根据地址是否匹配缺陷地址来改变时钟的第二阶段中的第一节点的逻辑电平。时钟延迟部分延迟时钟。驱动部分接收地址确定部分的输出和时钟延迟部分的输出，并产生冗余字线驱动信号。

3. 发明授权

US08736532B2 Liquid crystal display device having a 1-dot inversion or 2-dot inversion scheme and method thereof 有权
标题翻译：具有1点反转或2点反转方案的液晶显示装置及其方法
公开(公告)号：US08736532B2
公开(公告)日：2014-05-27
申请号：US13333140
申请日：2011-12-21
申请人： Seung-Cheol Oh
发明人： Seung-Cheol Oh
IPC分类号： G09G3/36
CPC分类号： G09G3/2092 , G09G3/3648
摘要： A liquid crystal display device includes a liquid crystal panel including a plurality of gate lines (GL1 to GLn) data lines (DL1 to DLm) and a plurality of pixel areas; a timing controller arranging the external input image data to be proper to the driving of the liquid crystal panel, generating a gate control signal (GCS) and a data control signal (DCS), and grouping the arranged image data into a plurality of groups each having a plurality of controller channels, and outputting a group control signal (HINV_m) by determining whether the arranged image data for each group is proper to horzintal-1-dot inversion or horizontal-2-dot inversion; a gate driver driving the plurality of the gate lines of the liquid crystal panel based on the gate control signal (GCS) from the timing controller; and a data driver grouping output terminals into a plurality of groups.
摘要翻译：液晶显示装置包括：液晶面板，包括多条栅极线（GL1〜GLn），数据线（DL1〜DLm）和多个像素区域; 定时控制器，将外部输入图像数据配置为适合于液晶面板的驱动，产生门控制信号（GCS）和数据控制信号（DCS），并将排列的图像数据分组成多个组具有多个控制器通道，并且通过确定每组的排列图像数据是否适合于水平1点反转或水平2点反转来输出组控制信号（HINV_m）; 基于来自定时控制器的栅极控制信号（GCS）驱动液晶面板的多条栅极线的栅极驱动器; 以及将输出终端分组成多个组的数据驱动器。

4. 发明授权

US06741515B2 DRAM with total self refresh and control circuit 失效
标题翻译： DRAM具有全自动刷新和控制电路
公开(公告)号：US06741515B2
公开(公告)日：2004-05-25
申请号：US10174867
申请日：2002-06-18
申请人： Paul S. Lazar , Seung Cheol Oh
发明人： Paul S. Lazar , Seung Cheol Oh
IPC分类号： G11C700
CPC分类号： G11C11/40603 , G11C11/406 , G11C11/40615
摘要： Internally refreshing one or more DRAM arrays without requiring additional external command signals. Scheduling of either refresh cycles and/or read/write access cycles uses an arbitration and selection circuit that receives a refresh request input signal from an independent oscillator and a row access select RAS input signal. A wordline address multiplexer provides either internally-provided refresh or externally-provided row-line address signals to a wordline decoder. A refresh row counter uses a token status signal for activating only one refresh row counter at a time. Instantaneous refresh power is controlled by controlling the number of cells in each DRAM block. An arbitration and control system includes an address transition block with a delay for resolving metastability, a refresh control block, a RAS control block, and an arbitration circuit that temporarily stores unselected requests.
摘要翻译：内部刷新一个或多个DRAM阵列，而不需要额外的外部命令信号。刷新周期和/或读/写访问周期的调度使用仲裁和选择电路，其接收来自独立振荡器的刷新请求输入信号和行访问选择RAS输入信号。字线地址复用器将内部提供的刷新或外部提供的行行地址信号提供给字线解码器。刷新行计数器使用令牌状态信号一次仅激活一个刷新行计数器。通过控制每个DRAM块中的单元数量来控制瞬时刷新功率。仲裁和控制系统包括具有用于解决亚稳态的延迟的地址转换块，刷新控制块，RAS控制块和临时存储未选择的请求的仲裁电路。

5. 发明授权

US5396465A Circuit for controlling isolation transistors in a semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的隔离晶体管的电路
公开(公告)号：US5396465A
公开(公告)日：1995-03-07
申请号：US156779
申请日：1993-11-24
申请人： Seung-Cheol Oh , Yong-Sik Seok
发明人： Seung-Cheol Oh , Yong-Sik Seok
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C7/1006 , G11C29/50 , G11C11/401
摘要： A semiconductor memory device has adjacent memory arrays and isolation transistors disposed between a common bit sense amplifier and the memory arrays. An isolation control circuit according the present invention generates the power supply voltage Vcc (not the boost voltage Vpp) during the burn-in mode of operation, so that the gate oxide layer of the isolation transistors is prevented from being destroyed or deteriorated.
摘要翻译：半导体存储器件具有设置在公共位读出放大器和存储器阵列之间的相邻存储器阵列和隔离晶体管。根据本发明的隔离控制电路在老化操作模式期间产生电源电压Vcc（而不是升压电压Vpp），从而防止隔离晶体管的栅极氧化层被破坏或劣化。

6. 发明申请

US20120162178A1 LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME 有权
标题翻译：液晶显示装置及其驱动方法
公开(公告)号：US20120162178A1
公开(公告)日：2012-06-28
申请号：US13333140
申请日：2011-12-21
申请人： Seung-Cheol OH
发明人： Seung-Cheol OH
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/2092 , G09G3/3648
摘要： A liquid crystal display device includes a liquid crystal panel including a plurality of gate lines (GL1 to GLn) data lines (DL1 to DLm) and a plurality of pixel areas; a timing controller arranging the external input image data to be proper to the driving of the liquid crystal panel, generating a gate control signal (GCS) and a data control signal (DCS), and grouping the arranged image data into a plurality of groups each having a plurality of controller channels, and outputting a group control signal (HINV_m) by determining whether the arranged image data for each group is proper to horzintal-1-dot inversion or horizontal-2-dot inversion; a gate driver driving the plurality of the gate lines of the liquid crystal panel based on the gate control signal (GCS) from the timing controller; and a data driver grouping output terminals into a plurality of groups.
摘要翻译：液晶显示装置包括：液晶面板，包括多条栅极线（GL1〜GLn），数据线（DL1〜DLm）和多个像素区域; 定时控制器，将外部输入图像数据配置为适合于液晶面板的驱动，产生门控制信号（GCS）和数据控制信号（DCS），并将排列的图像数据分组成多个组具有多个控制器通道，并且通过确定每组的排列图像数据是否适合于水平1点反转或水平2点反转来输出组控制信号（HINV_m）; 基于来自定时控制器的栅极控制信号（GCS）驱动液晶面板的多条栅极线的栅极驱动器; 以及将输出终端分组成多个组的数据驱动器。

7. 发明授权

US06981187B1 Test mode for a self-refreshed SRAM with DRAM memory cells 失效
标题翻译：具有DRAM存储单元的自刷新SRAM的测试模式
公开(公告)号：US06981187B1
公开(公告)日：2005-12-27
申请号：US10290045
申请日：2002-11-06
申请人： Seung Cheol Oh
发明人： Seung Cheol Oh
IPC分类号： G11C29/00 , G11C29/50
CPC分类号： G11C29/50016 , G11C11/401 , G11C29/50
摘要： A self-refreshing SRAM with internal DRAM memory cells is provided with a test mode enable circuit for testing the real refresh time of the internal SRAM memory cells and for determining the maximum refresh capability of the internal DRAM memory cells. The self-refreshing DRAM includes a test-mode enable circuit, an arbitration circuit, and a memory control logic circuit. In a normal mode of operation, the test mode enable circuit is not active. In a test mode of operation, the test mode enable circuit is active which enables the memory control logic to be controlled by an external command signal that is provided through an external pin, such as a chip-enable /CE pin when the chip is in the test mode.
摘要翻译：具有内部DRAM存储单元的自刷新SRAM提供有测试模式使能电路，用于测试内部SRAM存储单元的实际刷新时间并确定内部DRAM存储单元的最大刷新能力。自刷新DRAM包括测试模式使能电路，仲裁电路和存储器控制逻辑电路。在正常工作模式下，测试模式使能电路无效。在测试操作模式下，测试模式使能电路是有效的，这使得存储器控制逻辑可以通过外部指令信号来控制，外部指令信号通过外部引脚提供，例如芯片使能/ CE引脚时的芯片使能/ CE引脚测试模式。

8. 发明授权

US06735142B1 Power-up control circuit with a power-saving mode of operation 失效
标题翻译：上电控制电路具有省电模式运行
公开(公告)号：US06735142B1
公开(公告)日：2004-05-11
申请号：US10263372
申请日：2002-10-01
申请人： Seung Cheol Oh
发明人： Seung Cheol Oh
IPC分类号： G11C700
CPC分类号： G11C7/20 , G11C7/22 , G11C2207/2227
摘要： A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide an improved, combined power-up control signal CPWRUP. The combined power-up control signal CPWRUP signal is temporarily brought to a LOW state for a predetermined period of time immediately after the end of a power-saving mode of operation, such as a deep-sleep mode of operation for a memory device. The LOW state of the combined power-up control signal CPWRUP output signal allows all internal circuitry to be returned to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.
摘要翻译：上电控制电路具有包括正常电源电压电平检测部分，用于检测深度睡眠使能输入信号的特殊命令部分和逻辑地组合正常电源电压检测部分的输出信号的三个部件，电源电压检测部分和特殊指令检测部分，以提供改进的组合上电控制信号CPWRUP。组合的上电控制信号CPWRUP信号在诸如用于存储器件的深度睡眠操作模式的功率保存操作模式结束之后的预定时间段内暂时进入LOW状态。组合的上电控制信号CPWRUP输出信号的LOW状态允许所有内部电路返回到与正常上电序列之后获得的初始状态相同的初始状态，即使外部电压电平保持在其正常状态水平。

9. 发明授权

US6060942A Voltage boosting power supply circuit of memory integrated circuit and method for controlling charge amount of voltage boosting power supply 失效
标题翻译：存储器集成电路的升压电源电路以及用于控制升压电源的充电量的方法
公开(公告)号：US6060942A
公开(公告)日：2000-05-09
申请号：US64698
申请日：1998-04-22
申请人： Seung-cheol Oh
发明人： Seung-cheol Oh
IPC分类号： G11C11/413 , G05F1/62 , G11C11/40 , G11C11/407 , H01L21/822 , H01L27/04 , H02M3/07 , G05F1/10
CPC分类号： G05F1/62
摘要： A voltage boosting power supply circuit of a memory integrated circuit and a method for controlling charge amount of a voltage boosting power supply. The voltage boosting power supply circuit includes first and second power suppliers, first and second fuses, a voltage boosting controller, a voltage boosting enabling unit, and a voltage booster. The first and second power suppliers supply power supply. Each of one ends of the first and second fuses is connected to the first and second power suppliers. The voltage boosting controller generates first and second control signals a voltage boosting controller for generating first and second control signals, responding to a voltage boosting control signal which is in a ground voltage state before signals generated from each of other ends of the first and second fuses and the power supply become stable, and becomes logic high when the power supply becomes stable. The voltage boosting enabling unit generates the third to fifth control signals, responding to the first and second control signals and the voltage boosting enable signal. The voltage booster generates the voltage boosting power supply, responding to the third to fifth control signals.
摘要翻译：存储器集成电路的升压电源电路和用于控制升压电源的充电量的方法。升压电源电路包括第一和第二电源，第一和第二保险丝，升压控制器，升压启动单元和升压器。第一和第二电力供应商提供电源。第一和第二熔断器的一端各自连接到第一和第二电源。升压控制器产生第一和第二控制信号，升压控制器用于产生第一和第二保险丝的每个其它端的信号产生的信号之前响应于处于接地电压状态的升压控制信号的第一和第二控制信号电源稳定，电源稳定时变为逻辑高电平。升压启动单元根据第一和第二控制信号和升压启动信号产生第三至第五控制信号。升压器产生升压电源，响应第三至第五控制信号。

10. 发明授权

US06643216B1 Asynchronous queuing circuit for DRAM external RAS accesses 失效
标题翻译：用于DRAM外部RAS访问的异步排队电路
公开(公告)号：US06643216B1
公开(公告)日：2003-11-04
申请号：US10211952
申请日：2002-08-02
申请人： Paul S. Lazar , Seung Cheol Oh
发明人： Paul S. Lazar , Seung Cheol Oh
IPC分类号： G11C800
CPC分类号： G11C7/109 , G11C7/1078 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/408 , G11C11/4096
摘要： A method and queuing circuit are provided for storing asynchronous external RAS access requests and for executing corresponding RAS cycles. When no current external access RAS cycle is currently underway a first request latch or similar storage element is set in response to an initial access request. When access to the memory begins in a RAS cycle, this first request latch is reset. When a RAS cycle is currently underway, a second request-queuing latch is set in response to a new, second access request that occurs. Whenever a RAS cycle is completed, if the second queuing latch is set, a new RAS cycle is initiated and both the first and the second latches are reset. Any subsequent new access request may then be queued if the subsequent new access request arrives prior to completion of the current second access cycle.
摘要翻译：提供了一种方法和排队电路，用于存储异步外部RAS访问请求并用于执行相应的RAS周期。当当前没有当前的外部访问RAS周期正在进行时，响应于初始访问请求设置第一请求锁存器或类似的存储元件。当在RAS周期中开始访问存储器时，该第一个请求锁存器被复位。当RAS周期当前正在进行时，响应于发生的新的第二访问请求而设置第二请求排队锁存器。无论何时完成RAS周期，如果设置了第二个排队锁存器，将启动一个新的RAS周期，并重置第一个和第二个锁存器。如果随后的新访问请求在当前第二访问周期完成之前到达，则随后的新访问请求可以被排队。

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