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1. 发明授权

US5315557A Semiconductor memory device having self-refresh and back-bias circuitry 失效
标题翻译：具有自刷新和反向偏置电路的半导体存储器件
公开(公告)号：US5315557A
公开(公告)日：1994-05-24
申请号：US980951
申请日：1992-11-25
申请人： Moon-Gone Kim , Sei-Seung Yoon
发明人： Moon-Gone Kim , Sei-Seung Yoon
IPC分类号： G11C11/403 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/402 , G11C7/02
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes a refresh timer for generating a refresh clock pulse, a binary counter for generating a predetermined number of signals of different frequencies and a circuit for generating a self-refresh enable signal in response to the signal transmitted from the binary counter. A back-bias clock pulse generator is also included having first, second and third selectors, of which the third selector selects one of the signals transmitted from the binary counter in response to a signal output from each of the first and second selectors. A back-bias generator having an oscillator and a back-bias voltage detecting circuit and a selection circuit for receiving the output signal from the back-bias voltage detection circuit is attached thereto. A signal is transmitted to the oscillator in response to the self-refresh enable signal. The oscillator output, together with the output of the back-bias control pulse generator, cause a driver control circuit to feed a drive signal to a charge pump during a self-refresh operation.
摘要翻译：半导体存储器件包括用于产生刷新时钟脉冲的刷新定时器，用于产生预定数量的不同频率的信号的二进制计数器和用于响应于从二进制计数器发送的信号产生自刷新使能信号的电路。还包括背偏置时钟脉冲发生器，其具有第一，第二和第三选择器，其中第三选择器响应于从第一和第二选择器中的每个选择器输出的信号，选择从二进制计数器发送的信号之一。具有振荡器和背偏电压检测电路的背偏置发生器和用于从反偏压检测电路接收输出信号的选择电路。响应于自刷新使能信号，信号被发送到振荡器。振荡器输出与反向偏置控制脉冲发生器的输出一起导致驱动器控制电路在自刷新操作期间将驱动信号馈送到电荷泵。

2. 发明授权

US06721220B2 Bit line control and sense amplification for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的位线控制和读出放大
公开(公告)号：US06721220B2
公开(公告)日：2004-04-13
申请号：US10191686
申请日：2002-07-05
申请人： Sei-Seung Yoon , Seong-Ook Jung
发明人： Sei-Seung Yoon , Seong-Ook Jung
IPC分类号： G11C700
CPC分类号： G11C11/39
摘要： A circuit and a method are provided for facilitating control of bit lines in preparation for, or during, sense amplification of data signals from thinly capacitively-coupled thyristor (“TCCT”)-based memory cells. In accordance with a specific embodiment, a circuit and method are designed, among other things, to effectively minimize power consumption by memory cells and to increase speed and reliability of sense amplification. In another specific embodiment, the circuit and method are directed to TCCT-based memory cells.
摘要翻译：提供了一种电路和方法，用于促进对位线的控制，以准备或在其期间从来自薄电容耦合晶闸管（“TCCT”）的存储器单元的数据信号的感测放大。根据具体实施例，除其他之外，设计电路和方法以有效地最小化存储器单元的功耗并增加感测放大的速度和可靠性。在另一具体实施例中，电路和方法针对基于TCCT的存储器单元。

3. 发明授权

US5781494A Voltage pumping circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的电压泵浦电路
公开(公告)号：US5781494A
公开(公告)日：1998-07-14
申请号：US782896
申请日：1996-12-27
申请人： Yong-Cheol Bae , Sei-Seung Yoon , Dong-Il Seo
发明人： Yong-Cheol Bae , Sei-Seung Yoon , Dong-Il Seo
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C11/407 , H01L21/8242 , H01L27/108 , G11C8/00
CPC分类号： G11C5/145
摘要： A semiconductor memory device comprising a memory cell array including at least two banks and a desired number of voltage pumping circuits each for pumping an input voltage to a desired level. The voltage pumping circuits are driven in response to at least two bank selection control signals. The voltage pumping circuits are arranged in the semiconductor memory device in a proper manner to efficiently perform the voltage pumping operation, so as to increase the pumping efficiency. Further, the proper arrangement of the voltage pumping circuits contributes to the integration of the semiconductor memory device.
摘要翻译：一种半导体存储器件，包括存储单元阵列，该存储单元阵列包括至少两个存储体和所需数量的电压泵浦电路，每个用于将输入电压泵送到期望的电平。电压泵浦电路响应于至少两个存储体选择控制信号被驱动。电压泵浦电路以适当的方式布置在半导体存储器件中，以有效地执行电压泵送操作，从而提高泵送效率。此外，电压泵浦电路的适当布置有助于半导体存储器件的集成。

4. 发明授权

US07324394B1 Single data line sensing scheme for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的单数据线感测方案
公开(公告)号：US07324394B1
公开(公告)日：2008-01-29
申请号：US11360181
申请日：2006-02-23
申请人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
发明人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/08 , G11C7/12 , G11C7/14
摘要： A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
摘要翻译：本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供偏置到位线，以及被配置为至少一个预定电平的参考节点。在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为应用于位线。

5. 发明授权

US06184078B2 Method for fabricating a capacitor for a dynamic random access memory cell 有权
标题翻译：制造用于动态随机存取存储单元的电容器的方法
公开(公告)号：US06184078B2
公开(公告)日：2001-02-06
申请号：US09170086
申请日：1998-10-13
申请人： Sei-Seung Yoon , Yong-Cheol Bae
发明人： Sei-Seung Yoon , Yong-Cheol Bae
IPC分类号： H01L218242
CPC分类号： H01L27/10855 , H01L27/10814
摘要： A method for fabricating a DRAM cell capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate wherein a storage node is formed on a buried contact pad in self-alignment. The method comprises forming a second insulator layer on the first insulator layer including the buried contact pad. An etching stopper layer is next formed on the second insulator layer. Sequentially, a third insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the third insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on both sidewalls of the top via hole. After removal of the masking layer, the etching stopper layer and the second insulator layer are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized by CMP procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the cylindrical storage node having the sidewall spacer and the second polysilicon layer in self-alignment.
摘要翻译：一种用于制造DRAM单元电容器的方法可应用于半导体衬底上的高密度动态随机存取存储器（DRAM）器件，其中存储节点以自对准方式形成在埋地接触焊盘上。该方法包括在包括埋入接触垫的第一绝缘体层上形成第二绝缘体层。接着在第二绝缘体层上形成蚀刻阻挡层。接着，在蚀刻阻挡层上形成第三绝缘体层和第一多晶硅层。在第一多晶硅层上形成掩模层以限定存储节点。使用掩模层依次蚀刻第一多晶硅层和第三绝缘体层，直到蚀刻停止层露出为止，形成顶部通孔。侧壁间隔件形成在顶部通孔的两个侧壁上。在去除掩模层之后，使用第一多晶硅层和侧壁间隔物的组合作为掩模，依次蚀刻蚀刻停止层和第二绝缘体层，直到接触焊盘露出，以便在下面形成底部通孔顶部通孔。沉积第二多晶硅层，填充底部和顶部通孔。半导体衬底通过CMP工艺平坦化，直到暴露第三绝缘体层。最后，蚀刻第三绝缘体层以形成具有侧壁间隔物和第二多晶硅层自对准的圆柱形存储节点。

6. 发明授权

US5677877A Integrated circuit chips with multiplexed input/output pads and methods of operating same 失效
标题翻译：具有复用输入/输出焊盘的集成电路芯片及其操作方法
公开(公告)号：US5677877A
公开(公告)日：1997-10-14
申请号：US651375
申请日：1996-05-22
申请人： Sei-Seung Yoon , Tae-Seong Jang
发明人： Sei-Seung Yoon , Tae-Seong Jang
IPC分类号： G11C11/41 , G11C5/06 , G11C11/407 , G11C29/00 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C7/00 , G11C8/00
CPC分类号： G11C29/808 , G11C29/84 , G11C5/066
摘要： Integrated circuit chips with multiplexed input/output pads include means for expanding the functional and diagnostic capability of the circuit by increasing the effective number of input/output pads connected thereto so that more information can be provided to and from the chip. In particular, multiplexing means preferably provides the capability of accessing any one of a plurality of signal lines in the circuit from each input/output pad. This expanded capability is preferably achieved using one or more selection control signals which can be generated internally or externally to a chip containing the integrated circuit. An integrated circuit memory device, for example, preferably comprises a semiconductor substrate, a memory circuit in the substrate, a plurality of input/output pads and means, coupled to signal lines in the memory circuit, for multiplexing the plurality of input/output pads to the signal lines by electrically connecting respective ones of the signal lines to the input/output pads in response to a first select signal and electrically connecting respective others of the signal lines to the input/output pads in response to a second select signal. Because each pad on a chip can be connected to one or more signal lines, the memory circuit has a greater number of effective pads which means that a fewer number of pads on a small memory circuit chip can provide essentially the same input/output capability as a greater number of pads on a larger chip.
摘要翻译：具有复用输入/输出焊盘的集成电路芯片包括通过增加连接到其上的输入/输出焊盘的有效数量来扩展电路的功能和诊断能力的装置，以便可以向芯片提供更多的信息。具体地，复用装置优选地提供从每个输入/输出焊盘访问电路中的多条信号线中的任何一条的能力。该扩展能力优选地使用可以在包含集成电路的芯片的内部或外部产生的一个或多个选择控制信号来实现。例如，集成电路存储器件优选地包括半导体衬底，衬底中的存储器电路，耦合到存储器电路中的信号线的多个输入/输出焊盘和装置，用于多路复用多个输入/输出焊盘通过响应于第一选择信号将相应的信号线电连接到输入/输出焊盘并且响应于第二选择信号将各个信号线电连接到输入/输出焊盘而将信号线连接到信号线。因为芯片上的每个焊盘可以连接到一个或多个信号线，所以存储器电路具有更多数量的有效焊盘，这意味着小存储器电路芯片上较少数量的焊盘可以提供基本相同的输入/输出能力更大数量的焊盘在更大的芯片上。

7. 发明授权

US5579276A Internal voltage boosting circuit in a semiconductor memory device 失效
标题翻译：半导体存储器件中的内部升压电路
公开(公告)号：US5579276A
公开(公告)日：1996-11-26
申请号：US542965
申请日：1995-10-13
申请人： Sei-Seung Yoon , Byung-Chul Kim
发明人： Sei-Seung Yoon , Byung-Chul Kim
IPC分类号： G11C11/407 , G11C5/14 , H01L27/10 , H02M3/07 , H03K19/00 , G11C7/00
CPC分类号： G11C5/145
摘要： The voltage boosting circuit of the present invention includes a voltage converting circuit connected between an oscillator and a pair of pumping capacitors. The pair of pumping capacitors are then connected to a single transmission transistor, which outputs a boosted voltage that is derived from the combination of a precharge voltage placed on the source of the transmission transistor and the voltage stored on the pumping capacitors. The presence of the voltage converting circuit, which uses cross-connected PMOS transistors coupled to ground through a pair of NMOS transistors and establishes a differential amplifier, substantially eliminates the body effect problems that would otherwise occur.
摘要翻译：本发明的升压电路包括连接在振荡器和一对泵浦电容器之间的电压转换电路。然后，该对泵浦电容器连接到单个传输晶体管，其输出从放置在传输晶体管的源极上的预充电电压与存储在泵浦电容器上的电压的组合导出的升压电压。使用通过一对NMOS晶体管耦合到地并且建立差分放大器的交叉连接的PMOS晶体管的电压转换电路的存在基本上消除了否则将发生的体效应问题。

8. 发明授权

US06903987B2 Single data line sensing scheme for TCCT-based memory cells 失效
标题翻译：基于TCCT的存储单元的单数据线感测方案
公开(公告)号：US06903987B2
公开(公告)日：2005-06-07
申请号：US10211766
申请日：2002-08-01
申请人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
发明人： Sei-Seung Yoon , Jin-Man Han , Seong-Ook Jung
IPC分类号： G11C11/00 , G11C11/39 , H01L21/8244 , H01L27/11 , H01L31/111
CPC分类号： H01L27/11 , G11C11/39
摘要： A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as VDD. One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
摘要翻译：本文公开了一种包括用于解析由存储器单元产生的数据信号的读出放大器的感测电路。感测电路包括用于接收数据信号的位线，耦合到位线并被配置为对位线预充电的第一预充电器件，用于提供耦合到位线的偏置并被配置为提供偏置到位线，以及被配置为至少一个预定电平的参考节点。在一个实施例中，预定电平等于诸如地电位的低电位，而在另一实施例中等于诸如V DD的高电位。一个或多个开关装置允许激活或去激活预充电装置，允许将位线预充电到特定电位，感测电路快速而准确地确定逻辑状态“1”或“0”是否为应用于位线。

9. 发明授权

US06735113B2 Circuit and method for implementing a write operation with TCCT-based memory cells 失效
标题翻译：用于基于TCCT的存储单元实现写入操作的电路和方法
公开(公告)号：US06735113B2
公开(公告)日：2004-05-11
申请号：US10272360
申请日：2002-10-15
申请人： Sei-Seung Yoon , Seong-Ook Jung
发明人： Sei-Seung Yoon , Seong-Ook Jung
IPC分类号： G11C1134
CPC分类号： G11C11/39
摘要： The present invention provides a circuit and a method for providing nondestructive write operations and optimized memory access operations with reduced power consumption during memory access, such as during write operations. In one embodiment, a memory device comprises a memory cell configured to store a first data bit. The memory device also comprises a write access circuit coupled to the memory cell for providing a write data bit having a write data bit magnitude. The write access circuit is configured to adjust the write data bit magnitude to an intermediate logic state magnitude in a memory operation.
摘要翻译：本发明提供一种电路和方法，用于在存储器访问期间（例如在写入操作期间）以降低的功耗提供非破坏性写入操作和优化的存储器访问操作。在一个实施例中，存储器设备包括被配置为存储第一数据位的存储器单元。存储器件还包括耦合到存储器单元的写存取电路，用于提供具有写数据位幅值的写数据位。写访问电路被配置为在存储器操作中将写入数据位幅度调整到中间逻辑状态幅度。

10. 发明授权

US5608677A Boosting voltage circuit used in active cycle of a semiconductor memory device 失效
标题翻译：在半导体存储器件的有效周期中使用的升压电路
公开(公告)号：US5608677A
公开(公告)日：1997-03-04
申请号：US579913
申请日：1995-12-28
申请人： Sei-Seung Yoon , Chan-Jong Park , Byung-Chul Kim
发明人： Sei-Seung Yoon , Chan-Jong Park , Byung-Chul Kim
IPC分类号： G11C5/14 , G11C7/00
CPC分类号： G11C5/145
摘要： A voltage boosting circuit for a semiconductor memory device has a clock generator for supplying a chip master clock determining an active state and a stand-by state in respective response to first and second states thereof, for generating a detector control signal a first delay time after the first state of the chip master clock is generated, and for generating a latch control signal a second delay time after the first state of the chip master clock is generated. A boosting voltage detector responds to the detector control signal and the latch control signal to generate a detecting signal indicative of a current state of a boosting voltage potential. First and second boosting voltage generators generate the boosting voltage potential, respectively operating in the stand-by state and active state in accordance with the detecting signal and delayed chip master clock signal.
摘要翻译：一种用于半导体存储器件的升压电路具有一个时钟发生器，用于在分别响应于其第一和第二状态提供确定有效状态和待机状态的芯片主时钟，以产生检测器控制信号，该第一延迟时间在产生芯片主时钟的第一状态，并且用于在产生芯片主时钟的第一状态之后产生锁存控制信号第二延迟时间。升压电压检测器响应于检测器控制信号和锁存控制信号，以产生指示升压电压电位的当前状态的检测信号。第一和第二升压电压发生器根据检测信号和延迟芯片主时钟信号产生升压电压，分别工作在待机状态和有效状态。

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