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    • 1. 发明授权
      US06476652B1 Delay locked loop for use in synchronous dynamic random access memory 有权
    • Delay locked loop for use in synchronous dynamic random access memory
    • 延迟锁定环用于同步动态随机存取存储器
    • US06476652B1
    • 2002-11-05
    • US09703406
    • 2000-10-31
    • Seong-Hoon Lee , Jung-Il Yang
    • Seong-Hoon Lee , Jung-Il Yang
    • H03L700
    • G11C7/222 , G11C7/22
    • A delay locked loop (DLL) is used to compensate for a skew in a synchronous dynamic random access memory. The delay locked loop includes: a delay model for delaying an external clock signal by the skew to generate a delayed clock signal; a signal generation unit, in response to the external clock signal and the delayed clock signal, for generating control signals; a first delay unit, in response to the control signals, for delaying the delayed control signal to generate a first DLL clock signal, wherein the first delay unit has a large unit delay; and a second delay unit, in response to the control signals, for delaying the first DLL clock signal to generate a second DLL clock signal, wherein the second delay means in a small unit delay.
    • 延迟锁定环（DLL）用于补偿同步动态随机存取存储器中的偏斜。 延迟锁定环包括：用于通过偏斜延迟外部时钟信号以产生延迟的时钟信号的延迟模型; 信号生成单元，响应于所述外部时钟信号和所述延迟的时钟信号，用于产生控制信号; 第一延迟单元，响应于所述控制信号，用于延迟所述延迟的控制信号以产生第一DLL时钟信号，其中所述第一延迟单元具有大的单位延迟; 以及响应于所述控制信号的第二延迟单元，用于延迟所述第一DLL时钟信号以产生第二DLL时钟信号，其中所述第二延迟装置以小的单位延迟。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 6. 发明申请
      US20060244492A1 Method of producing balanced data output 有权
    • Method of producing balanced data output
    • 产生平衡数据输出的方法
    • US20060244492A1
    • 2006-11-02
    • US11114130
    • 2005-04-26
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • H03K5/22
    • H03K5/04 , H03K5/135 , H03K5/26
    • Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.
    • 选通信号耦合到相位检测器，该相位检测器比较各个选通信号的上升沿和下降沿。 如果相位检测器确定存在不匹配，则向控制电路输出UP或DOWN控制信号。 然后，控制电路将UP或DOWN控制信号发送到连接到每个选通脉冲的边缘调整电路和触发器和预驱动器之间的数据流。 边缘调整然后对每个相应的选通和数据流添加一个延迟，增量地补偿由PVT变化产生的失配。 重复该过程，直到高和低数据输出被有效地匹配，从而使数据眼睛最大化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明申请
      US20060176761A1 Clock generating circuit with multiple modes of operation 有权
    • Clock generating circuit with multiple modes of operation
    • 具有多种工作模式的时钟发生电路
    • US20060176761A1
    • 2006-08-10
    • US11054885
    • 2005-02-09
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • G11C8/00
    • G11C7/1072 , G11C7/222 , H03L7/0812 , H03L7/095 , H03L7/0995
    • A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.
    • 时钟发生电路包括相位比较电路，该相位比较电路产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06434062B1 Delay locked loop for use in semiconductor memory device 有权
    • Delay locked loop for use in semiconductor memory device
    • US06434062B1
    • 2002-08-13
    • US09745490
    • 2000-12-21
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • G11C700
    • It is provided a delay locked loop for obtaining a reduced jitter and a stable time delay adjustment to thereby perform a bi-directional time delay with a small area even at low frequency applications. The delay locked loop includes an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal, a controller for receiving the internal clock to produce a control signal, a bi-directional oscillator, responsive to the control signal from the control means, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay, a counter for receiving an output signal of the bi-directional oscillator and counting the number that the signal is passed therethrough, and an AND gate for performing a combination operation on the outputs of the bi-directional oscillating means and the counting means, to produce the result as a final internal clock signal.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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