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    • 5. 发明申请
    • VOLTAGE LEVEL TRANSLATOR AND METHOD
    • 电压水平翻译器和方法
    • US20100134146A1
    • 2010-06-03
    • US12327472
    • 2008-12-03
    • ONEGYUN NA
    • ONEGYUN NA
    • H03K19/0175H03L5/00
    • H03K3/356113
    • A level translator includes an NMOS input transistor and a PMOS input transistor having respective gates receiving an input voltage. The input transistors compare the input voltage to respective first and second supply voltages. The input voltage is also applied to an inverter that is powered by the first and second supply voltages. An output terminal is coupled to a third supply voltage through a PMOS output transistor and to a fourth supply voltage through an NMOS output transistor. The third and fourth supply voltages are outside of a range bounded by the first and second supply voltages. The respective drains of the input transistors and the output of the inverter are coupled to the gates of the output transistors in a manner that either turns the PMOS output transistor ON and the NMOS output transistor OFF or turns the NMOS output transistor ON and the PMOS output transistor OFF.
    • 电平转换器包括NMOS输入晶体管和具有接收输入电压的相应门极的PMOS输入晶体管。 输入晶体管将输入电压与相应的第一和第二电源电压进行比较。 输入电压也被施加到由第一和第二电源电压供电的逆变器。 输出端子通过PMOS输出晶体管耦合到第三电源电压,并通过NMOS输出晶体管耦合到第四电源电压。 第三和第四电源电压在由第一和第二电源电压限制的范围之外。 输入晶体管的各个漏极和反相器的输出端以这样的方式耦合到输出晶体管的栅极,使得PMOS输出晶体管导通,NMOS输出晶体管断开或使NMOS输出晶体管导通,PMOS输出 晶体管关闭。