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    • 5. 发明申请
      US20060244492A1 Method of producing balanced data output 有权
    • Method of producing balanced data output
    • 产生平衡数据输出的方法
    • US20060244492A1
    • 2006-11-02
    • US11114130
    • 2005-04-26
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • H03K5/22
    • H03K5/04 , H03K5/135 , H03K5/26
    • Strobe signals are coupled to a phase detector which compares rising and falling edges of the respective strobe signals. If the phase detector determines that there is a mismatch, it outputs an UP or DOWN control signal to a control circuit. The control circuit then transmits the UP or DOWN control signal to edge adjusting circuits connected to each strobe and data stream between the flip flop and pre-driver. The edge adjusting then adds a delay to each respective strobe and data stream which incrementally compensates for the mismatch created by PVT variations. The process is repeated until the high and low data outputs are effectively matched, thereby maximizing the data eye.
    • 选通信号耦合到相位检测器，该相位检测器比较各个选通信号的上升沿和下降沿。 如果相位检测器确定存在不匹配，则向控制电路输出UP或DOWN控制信号。 然后，控制电路将UP或DOWN控制信号发送到连接到每个选通脉冲的边缘调整电路和触发器和预驱动器之间的数据流。 边缘调整然后对每个相应的选通和数据流添加一个延迟，增量地补偿由PVT变化产生的失配。 重复该过程，直到高和低数据输出被有效地匹配，从而使数据眼睛最大化。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明申请
      US20060176761A1 Clock generating circuit with multiple modes of operation 有权
    • Clock generating circuit with multiple modes of operation
    • 具有多种工作模式的时钟发生电路
    • US20060176761A1
    • 2006-08-10
    • US11054885
    • 2005-02-09
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • G11C8/00
    • G11C7/1072 , G11C7/222 , H03L7/0812 , H03L7/095 , H03L7/0995
    • A clock generating circuit includes a phase comparison circuit that generates a delay control signal corresponding o the relative phases of an output clock signal and a reference clock signal. A voltage controlled delay circuit generates the delayed clock signal by inverting a signal applied to its input and delaying the signal by a delay that is determined by a delay control signal. A selection circuit couples either the reference clock signal or the delayed clock signal to the input of the voltage controlled delay circuit. When the reference clock signal is coupled to the input of the voltage controlled delay circuit, the clock generating circuit functions as a delay-lock loop. When the delayed clock signal is coupled to the input of the voltage controlled delay circuit, the voltage controlled delay circuit operates as a ring oscillator so that the clock generating circuit functions as a phase-lock loop.
    • 时钟发生电路包括相位比较电路，该相位比较电路产生对应于输出时钟信号和参考时钟信号的相对相位的延迟控制信号。 电压控制延迟电路通过反相施加到其输入的信号并延迟由延迟控制信号确定的延迟来产生延迟的时钟信号。 选择电路将参考时钟信号或延迟时钟信号耦合到电压控制延迟电路的输入端。 当参考时钟信号耦合到电压控制延迟电路的输入时，时钟发生电路用作延迟锁定环路。 当延迟时钟信号耦合到电压控制延迟电路的输入端时，电压控制延迟电路作为环形振荡器工作，使得时钟发生电路用作锁相环。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 9. 发明授权
      US06434062B1 Delay locked loop for use in semiconductor memory device 有权
    • Delay locked loop for use in semiconductor memory device
    • US06434062B1
    • 2002-08-13
    • US09745490
    • 2000-12-21
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • G11C700
    • It is provided a delay locked loop for obtaining a reduced jitter and a stable time delay adjustment to thereby perform a bi-directional time delay with a small area even at low frequency applications. The delay locked loop includes an input unit for receiving a clock signal and a non-clock signal and comparing received signals to produce an internal clock signal, a controller for receiving the internal clock to produce a control signal, a bi-directional oscillator, responsive to the control signal from the control means, for performing a ring oscillation in a first or second direction and fulfilling an addition and subtraction adjustment function for a time delay, a counter for receiving an output signal of the bi-directional oscillator and counting the number that the signal is passed therethrough, and an AND gate for performing a combination operation on the outputs of the bi-directional oscillating means and the counting means, to produce the result as a final internal clock signal.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 10. 发明授权
      US06342797B1 Delayed locked loop clock generator using delay-pulse-delay conversion 有权
    • Delayed locked loop clock generator using delay-pulse-delay conversion
    • 延迟锁定环时钟发生器采用延迟脉冲延迟转换
    • US06342797B1
    • 2002-01-29
    • US09475226
    • 1999-12-30
    • Seong-Hoon Lee
    • Seong-Hoon Lee
    • H03L706
    • G11C7/1066 , G06F1/10 , G11C7/22 , H03K5/133 , H03K5/135 , H03L7/0814 , H04L7/0337
    • A delayed locked loop (DLL) clock generator in DDR SDRAM is disclosed. The DLL clock generator comprises a pulse generator for generating a pulse signal of which a pulse width corresponds to a predetermined delay time; a first delay chain including a plurality of delay means, for delaying the pulse signal by a predetermined delay time in order; and a second delay chain having the same delay time as the first delay chain, for delaying an external clock signal responsive to an output signal from the delay means. The second clock signal is generated through the same path as a path through which the external clock signal is inputted and the delayed external clock signal is outputted.
    • 公开了DDR SDRAM中的延迟锁定环（DLL）时钟发生器。 所述DLL时钟发​​生器包括脉冲发生器，用于产生其脉冲宽度对应于预定延迟时间的脉冲信号; 包括多个延迟装置的第一延迟链，用于依次延迟脉冲信号预定的延迟时间; 以及具有与第一延迟链相同的延迟时间的第二延迟链，用于响应于来自延迟装置的输出信号来延迟外部时钟信号。 第二时钟信号通过与输入外部时钟信号的路径相同的路径产生，并且延迟的外部时钟信号被输出。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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